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A1010B-PQ100C

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
1-298
ACT 1 Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Input Module Propagation Delays ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3 V Speed
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
t
INYH
Pad to Y High 3.1 3.5 4.0 4.7 6.8 ns
t
INYL
Pad to Y Low 3.1 3.5 4.0 4.7 6.8 ns
Input Module Predicted Routing Delays
1
t
IRD1
FO=1 Routing Delay 0.9 1.1 1.2 1.4 2.0 ns
t
IRD2
FO=2 Routing Delay 1.4 1.7 1.9 2.2 3.2 ns
t
IRD3
FO=3 Routing Delay 2.1 2.5 2.8 3.3 4.8 ns
t
IRD4
FO=4 Routing Delay 3.1 3.6 4.1 4.8 7.0 ns
t
IRD8
FO=8 Routing Delay 6.6 7.7 8.7 10.2 14.8 ns
Global Clock Network
t
CKH
Input Low to High FO = 16
FO = 128
4.9
5.6
5.6
6.4
6.4
7.3
7.5
8.6
6.7
7.9 ns
t
CKL
Input High to Low FO = 16
FO = 128
6.4
7.0
7.4
8.1
8.4
9.2
9.9
10.8
8.8
10.0 ns
t
PWH
Minimum Pulse Width
High
FO = 16
FO = 128
6.5
6.8
7.5
8.0
8.5
9.0
10.0
10.5
8.9
9.8 ns
t
PWL
Minimum Pulse Width
Low
FO = 16
FO = 128
6.5
6.8
7.5
8.0
8.5
9.0
10.0
10.5
8.9
9.8 ns
t
CKSW
Maximum Skew FO = 16
FO = 128
1.2
1.8
1.3
2.1
1.5
2.4
1.8
2.8
1.5
2.4 ns
t
P
Minimum Period FO = 16
FO = 128
13.2
14.2
15.4
16.7
17.6
18.9
20.9
22.3
18.2
20 ns
f
MAX
Maximum Frequency FO = 16
FO = 128
75
70
65
60
57
53
48
45
55
50 MHz
Note:
1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns.
Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to
determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior
to shipment.
1-299
ACT
™
1 Series FPGAs
ACT 1 Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Output Module Timing ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3 V Speed
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
TTL Output Module Timing
1
t
DLH
Data to Pad High 6.7 7.6 8.7 10.3 15.0 ns
t
DHL
Data to Pad Low 7.5 8.6 9.8 11.5 16.7 ns
t
ENZH
Enable Pad Z to High 6.6 7.5 8.6 10.2 14.8 ns
t
ENZL
Enable Pad Z to Low 7.9 9.1 10.4 12.2 17.7 ns
t
ENHZ
Enable Pad High to Z 10.0 11.6 13.1 15.4 22.4 ns
t
ENLZ
Enable Pad Low to Z 9.0 10.4 11.8 13.9 20.2 ns
d
TLH
Delta Low to High 0.06 0.07 0.08 0.09 0.13 ns/pF
d
THL
Delta High to Low 0.08 0.09 0.10 0.12 0.17 ns/pF
CMOS Output Module Timing
1
t
DLH
Data to Pad High 7.9 9.2 10.4 12.2 17.7 ns
t
DHL
Data to Pad Low 6.4 7.2 8.2 9.8 14.2 ns
t
ENZH
Enable Pad Z to High 6.0 6.9 7.9 9.2 13.4 ns
t
ENZL
Enable Pad Z to Low 8.3 9.4 10.7 12.7 18.5 ns
t
ENHZ
Enable Pad High to Z 10.0 11.6 13.1 15.4 22.4 ns
t
ENLZ
Enable Pad Low to Z 9.0 10.4 11.8 13.9 20.2 ns
d
TLH
Delta Low to High 0.10 0.11 0.13 0.15 0.22 ns/pF
d
THL
Delta High to Low 0.06 0.07 0.08 0.09 0.13 ns/pF
Notes:
1. Delays based on 35 pF loading.
2. SSO information can be found in the “Simultaneous Switching Output Limits for Actel FPGAs” application note on page 4-125.
1-300
Notes:
1. NC: Denotes No Connection
2. All unlisted pin numbers are user I/Os.
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.
Package Pin Assignments
44-Pin PLCC
Signal
A1010B
Function
A1020B
Function
3 VCC VCC
10 GND GND
14 VCC VCC
16 VCC VCC
21 GND GND
25 VCC VCC
32 GND GND
33 CLK, I/O CLK, I/O
34 MODE MODE
35 VCC VCC
36 SDI, I/O SDI, I/O
37 DCLK, I/O DCLK, I/O
38 PRA, I/O PRA, I/O
39 PRB, I/O PRB, I/O
43 GND GND
44-Pin
PLCC
1 44
68-Pin PLCC
Signal
A1010B, A10V10B
Function
A1020B, A10V20B
Functions
4 VCC VCC
14 GND GND
15 GND GND
21 VCC VCC
25 VCC VCC
32 GND GND
38 VCC VCC
49 GND GND
52 CLK, I/O CLK, I/O
54 MODE MODE
55 VCC VCC
56 SDI, I/O SDI, I/O
57 DCLK, I/O DCLK, I/O
58 PRA, I/O PRA, I/O
59 PRB, I/O PRB, I/O
66 GND GND
68-Pin
PLCC
1 68
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

A1010B-PQ100C

Mfr. #:
Buy A1010B-PQ100C
Manufacturer:
Microchip / Microsemi
Description:
IC FPGA 57 I/O 100QFP
Lifecycle:
New from this manufacturer.
Delivery:
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