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LT3581IMSE#TRPBF

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LT3581
16
3581fb
For more information www.linear.com/LT3581
3581 F08
V
OUT
C
IN
B
A
SYNC
GND
A: RETURN C
IN
GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT
COMBINE C
IN
GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
B: RETURN C
OUT
AND C
OUT1
GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
TO NOT COMBINE C
OUT
AND C
OUT1
GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
SHDN
CLKOUT
+
–
V
IN
+
–
L1
17
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C
OUT1
R
GATE
C
OUT
D1
M1
D2
APPLICATIONS INFORMATION
LAYOUT GUIDELINES FOR BOOST, SEPIC, AND DUAL
INDUCTOR INVERTING TOPOLOGIES
General Layout Guidelines
• To optimize thermal performance, solder the exposed
ground pad of the LT3581 to the ground plane, with
multiple vias around the pad connecting to additional
ground planes.
• A ground plane should be used under the switcher circuitry
to prevent interplane coupling and overall noise.
• High speed switching path (see specific topology for
more information) must be kept as short as possible.
• The V
C
, FB, and RT components should be placed as
close to the LT3581 as possible, while being as far
away as practically possible from the switch node. The
ground for these components should be separated from
the switch current path.
• Place the bypass capacitor for the V
IN
pin as close as
possible to the LT3581.
• Place the bypass capacitor for the inductor as close as
possible to the inductor.
• The load should connect directly to the positive and
negative terminals of the output capacitor for best load
regulation.
Boost Topology Specific Layout Guidelines
• Keep length of loop (high speed switching path) gov
-
erning switch, diode D1, output capacitor C
OUT1
, and
ground return as short as possible to minimize parasitic
inductive spikes at the switch node during switching.
SEPIC Topology Specific Layout Guidelines
• Keep length of loop (high speed switching path) gov
-
erning switch, flying capacitor C1, diode D1, output
capacitor C
OUT
, and ground return as short as possible
to minimize parasitic inductive spikes at the switch node
during switching.
Inverting Topology Specific Layout Guidelines
• Keep ground return path from the cathode of D1 (to
chip) separated from output capacitor C
OUT
’s ground
return path (to chip) in order to minimize switching
noise coupling into the output.
• Keep length of loop (high speed switching path) govern-
ing switch, flying capacitor C1, diode D1, and ground
return as short as possible to minimize parasitic induc-
tive spikes at the switch node during switching.
Figure 8. Suggested Component Placement for Boost Topology
(MSOP Shown, DFN Similar, Not to Scale.) Pin 15 on DFN or
Pin 17 on MSOP Is the Exposed Pad Which Must Be Soldered
Directly to the Local Ground Plane for Adequate Thermal
Performance. Multiple Vias to Additional Ground Planes Will
Improve Thermal Performance
Figure 9. Suggested Component Placement for SEPIC Topology
(MSOP Shown, DFN Similar, Not to Scale.) Pin 15 on DFN or
Pin 17 on MSOP Is the Exposed Pad Which Must Be Soldered
Directly to the Local Ground Plane for Adequate Thermal
Performance. Multiple Vias to Additional Ground Planes Will
Improve Thermal Performance
3581 F09
V
OUT
C
IN
C1
D1
B
A
SYNC
GND
A: RETURN C
IN
AND L2 GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
TO NOT COMBINE C
IN
AND L2 GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
B: RETURN C
OUT
GROUNDS DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
TO NOT COMBINE C
OUT
GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
L1, L2: MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR IMPROVED
PERFORMANCE.
C
OUT
SHDN
CLKOUT
+
–
V
IN
+
–
•
•
L2
L1
17
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LT3581
17
3581fb
For more information www.linear.com/LT3581
APPLICATIONS INFORMATION
THERMAL CONSIDERATIONS
Overview
For the LT3581 to deliver its full output power, it is imp-
erative that a good thermal path be provided to dissipate
the heat generated within the package. This can be
accomplished by taking advantage of the thermal pad on
the underside of the IC. It is recommended that multiple
vias in the printed cir
cuit board be used to conduct heat
away from the IC and into a copper plane with as much
area as possible.
Power and Thermal Calculations
Power dissipation in the L
T3581 chip comes from four
primary sources: switch I
2
R losses, switch dynamic
losses, NPN base drive DC losses, and miscellaneous
input current losses. These formulas assume continuous
mode operation, so they should not be used for calculating
thermal losses or efficiency in discontinuous mode or at
light load currents.
The following example calculates the power dissipa
-
tion in the LT3581 for a particular boost application
(V
IN
= 5V, V
OUT
= 12V, I
OUT
= 0.83A, f
OSC
= 2MHz, V
D
= 0.45V,
V
CESAT
= 0.21V).
To calculate die junction temperature, use the appropriate
thermal resistance number and add in worst-case ambient
temperature:
T
J
= T
A
+ θ
JA
• P
TOTAL
Table 4. Power Calculations Example for Boost Converter with V
IN
= 5V, V
OUT
= 12V, I
OUT
= 0.83A, f
OSC
= 2MHz, V
D
= 0.45V, V
CESAT
= 0.21V
DEFINITION OF VARIABLES EQUATIONS DESIGN EXAMPLE VALUE
DC = SWITCH DUTY CYCLE
D
C =
V
OUT
– V
IN
+ V
D
V
OUT
+ V
D
– V
CESAT
DC =
12V – 5V + 0.45V
12V + 0.45V – 0.21V
DC = 60.9%
I
IN
= Average Switch Current
η = Power Conversion Efficiency
(typically 88% at high currents)
I
IN
=
V
OUT
• I
OUT
V
IN
• η
I
IN
=
12V •0.83A
5V • 0.88
I
IN
= 2.3A
P
SWDC
= Switch I
2
R Loss (DC)
R
SW
= Switch Resistance (typically
90mΩ combined SW1 and SW2)
P
SWDC
= DC • I
IN
2
• R
SW
P
SWDC
= 0.609 • (2.3A)
2
• 90mΩ
P
SWDC
= 290mW
P
SWAC
= Switch Dynamic Loss (AC)
P
SWAC
=13ns • I
IN
• V
OUT
• f
OSC
P
SWAC
= 13ns
( )
• 2.3A • 12V • 2MHz
( )
P
SWAC
= 718mW
P
BDC
= Base Drive Loss (DC)
P
BDC
=
V
IN
• I
IN
• DC
45
P
BDC
=
5V •2.3A • 0.609
45
P
BDC
= 156mW
P
INP
= Input Power Loss
P
INP
= 9mA • V
IN
P
INP
= 9mA • 5V
P
INP
= 45mW
P
TOTAL
= 1.209W
Figure 10. Suggested Component Placement for Dual Inductor
Inverting Topology (MSOP Shown, DFN Similar, Not to Scale.)
Pin 15 on DFN or Pin 17 on MSOP Is the Exposed Pad Which
Must Be Soldered Directly to the Local Ground Plane for
Adequate Thermal Performance. Multiple Vias to Additional
Ground Planes Will Improve Thermal Performance
3581 F10
C
IN
B
A
C
SYNC
GND
A: RETURN C
IN
GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
TO NOT COMBINE C
IN
GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
B: RETURN C
OUT
GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
TO NOT COMBINE C
OUT
GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
C: RETURN D1 GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED
TO NOT COMBINE D1 GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
L1, L2: MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR
IMPROVED PERFORMANCE.
C
OUT
SHDN
CLKOUT
– V
OUT
GND
V
IN
+
–
•
•
L2
L1
17
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C1
D1
LT3581
18
3581fb
For more information www.linear.com/LT3581
APPLICATIONS INFORMATION
where T
J
= Die Junction Temperature, T
A
= Ambient Tem-
perature, P
TOTAL
is the final result from the calculations
shown in Table 4, and θ
JA
is the thermal resistance from
the silicon junction to the ambient air.
The published (http://www.linear.com/designtools/pack
-
aging/Linear_Technology_Thermal_Resistance_Table.
pdf) θ
JA
value is 43°C/W for the 4mm × 3mm 14-pin DFN
package and 45°C/W for the 16-lead MSOP package. In
practice, lower θ
JA
values are realizable if board layout is
performed with appropriate grounding (accounting for heat
sinking properties of the board) and other considerations
listed in the Layout Guidelines section. For instance, a
θ
JA
value of ~24°C/W was consistently achieved for both
MSE and DFN packages of the LT3581 (at V
IN
= 5V, V
OUT
=
12V, I
OUT
= 0.83A, f
OSC
= 2MHz) when board layout was
optimized as per the suggestions in the Board Layout
Guidelines section.
Junction Temperature Measurement
The duty cycle of the CLKOUT signal is linearly propor
-
tional to die junction temperature, T
J
. To get a temperature
reading, measure the duty cycle of the CLKOUT signal and
use the following equation to approximate the junction
temperature:
T
J
=
DC
CLKOUT
– 35%
0.3%
where DC
CLKOUT
is the CLKOUT duty cycle in % and T
J
is the die junction temperature in °C. Although the actual
die temperature can deviate from the above equation by
±15°C, the relationship between change in CLKOUT duty
cycle and change in die temperature is well defined. Basi
-
cally a 1% change in CLKOUT duty cycle corresponds to a
3.33°C change in die temperature. Note
that the
CLKOUT
pin is only meant to drive capacitive loads up to 50pF.
Thermal Lockout
A fault condition occurs when the die temperature exceeds
165°C (see Operation Section), and the part goes into
thermal lockout. The fault condition ceases when the die
temperature drops by ~5°C (nominal).
SWITCHING FREQUENCY
There are several considerations in selecting the operat
-
ing frequency of the converter. The first is staying clear
of sensitive frequency bands, which cannot tolerate any
spectral noise. For example, in products incorporating RF
communications, the 455kHz IF frequency is sensitive to
any noise, therefore switching above 600kHz is desired.
Some communications have sensitivity to 1.1MHz and in
that
case a 1.5MHz switching converter frequency may be
employed. The second consideration is the physical size
of the converter. As the operating frequency goes up, the
inductor and filter capacitors go down in value and size.
The tradeoff is efficiency, since the losses due to switch
-
ing dynamics (see Thermal Considerations), Schottky
diode charge, and other capacitive loss terms increase
proportionally with frequency
.
Oscillator T
iming Resistor (R
T
)
The operating frequency of the LT3581 can be set by the
internal free-running oscillator. When the SYNC pin is driven
low (< 0.4V), the frequency of operation is set by a resistor
from the R
T
pin to ground. An internally trimmed timing
capacitor resides inside the IC. The oscillator frequency
is calculated using the following formula:
f
OSC
=
87.6
R
T
+ 1
where f
OSC
is in MHz and R
T
is in k. Conversely, R
T
(in k)
can be calculated from the desired frequency (in MHz)
using:
R
T
=
87.6
f
OSC
–
1
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LT3581IMSE#TRPBF

Mfr. #:
Buy LT3581IMSE#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 3A Boost/Inverting DC/DC Converter with Fault Protection
Lifecycle:
New from this manufacturer.
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