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X5083S8Z

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
10
FN8127.4
November 12, 2015
01234567
CS
SI
SCK
High Impedance
SO
Instruction
(1 Byte)
FIGURE 7. WREN/WRDI SEQUENCE
32 33 34 35 36 37 38 39
SCK
SI
CS
012345678910
SCK
SI
Instruction 16 Bit Address
Data Byte 1
76543210
CS
40 41 42 43 44 45 46 47
Data Byte 2
76543210
Data Byte 3
76543210
Data Byte N
15 14 13 3 2 1 0
20 21 22 23 24 25 26 27 28 29 30 31
654 321 0
FIGURE 8. EEPROM ARRAY WRITE SEQUENCE
0123456789
CS
SCK
SI
SO
High Impedance
Instruction
10 11 12 13 14 15
Data Byte
65
4
3210
W
D
1
W
D
0
B
L
2
L
1
L
0
BB
FIGURE 9. STATUS REGISTER WRITE SEQUENCE
X5083
11
FN8127.4
November 12, 2015
01234567
CS
SCK
SI
SO
SO MSB HIGH while
in the Nonvolatile write cycle
01234567
READ STATUS
INSTRUCTION
READ STATUS
INSTRUCTION
SO MSB still HIGH indicates
Nonvolatile write cycle still in progress
01234567
CS
SCK
SI
SO
01234567
READ STATUS
INSTRUCTION
READ STATUS
INSTRUCTION
1st detected SO MSB LOW
indicates end of Nonvolatile write cycle
43210
WD1
WD0
BL2
BL1
BL0
NONVOLATILE WRITE IN PROGRESS
NONVOLATILE
WRITE ENDS
FIGURE 10. READ NONVOLATILE WRITE STATUS
X5083
12
FN8127.4
November 12, 2015
Symbol Table
012345
CS
SCK
SI
INSTRUCTION
t
WC
Non-volatile
Write
Operation
67
NEXT
Wait t
WC
after a write for new operation,
if not using polling procedure
FIGURE 11. END OF NONVOLATILE WRITE (NO POLLING)
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
X5083
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

X5083S8Z

Mfr. #:
Buy X5083S8Z
Manufacturer:
Renesas / Intersil
Description:
Supervisory Circuits CPU SUP/WDT 8K SPI EE RST LW 5V+/-10%
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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