LT5575
13
5575f
APPLICATIONS INFORMATION
The LO input impedance and S11 parameters (without
external matching components) are listed in Table 2.
Table 2. LO Input Impedance
FREQUENCY
(GHz)
INPUT
IMPEDANCE (
Ω)
S11
MAG ANGLE (°)
0.8 9.6 +j 23.7 0.731 127.9
0.9 13 +j 27.1 0.669 120.4
1.0 17.9 +j 30 0.592 113.2
1.1 24.1 +j 31.7 0.508 106.1
1.2 31.2 +j 31.4 0.421 99.8
1.3 37.5 +j 28.9 0.341 95.1
1.4 41.9 +j 24.6 0.272 93.4
1.5 43.4 +j 20 0.221 96.2
1.6 42.9 +j 16.4 0.189 103.5
1.7 41.2 +j 14.1 0.18 113.1
1.8 39.5 +j 13.1 0.186 120.3
1.9 37.8 +j 13.1 0.201 124.5
2.0 36.6 +j 13.6 0.217 125.6
2.1 35.6 +j 14.6 0.236 125
2.2 35.1 +j 15.7 0.25 123.1
2.3 34.9 +j 17.1 0.264 120.1
2.4 35.1 +j 18.5 0.272 116.6
2.5 35.5 +j 19.9 0.281 113
2.6 36.3 +j 21.2 0.284 109
2.7 37.2 +j 22.5 0.287 105.1
I-Channel and Q-Channel Outputs
Each of the I-channel and Q-channel outputs is internally
connected to V
CC
through a 65Ω resistor. The output DC
bias voltage is V
CC
– 1.1V. The outputs can be DC-coupled
or AC-coupled to the external loads. Each single-ended
output has an impedance of 65Ω in parallel with a 5pF
internal capacitor, forming a low-pass fi lter with a –3dB
corner frequency at 490MHz. The loading resistance
on each output, R
LOAD
(single-ended), should be larger
than 300Ω to assure full gain. The gain is reduced by
20 • log
10
(1 + 65Ω/R
LOAD
) in dB when the output port is
terminated by R
LOAD
. For instance, the gain is reduced
by 7.23dB when each output pin is connected to a
50Ω load (or 100Ω differentially). The output should be
taken differentially (or by using differential-to-single-
ended conversion) for best RF performance, including
NF and IM2.
The phase relationship between the I-channel output signal
and the Q-channel output signal is fi xed. When the LO
input frequency is larger (or smaller) than the RF input
frequency, the Q-channel outputs (Q
OUT
+
, Q
OUT
) lead (or
lag) the I-channel outputs (I
OUT
+
, I
OUT
) by 90°.
When AC output coupling is used, the resulting high-
pass fi lter’s –3dB roll-off frequency is defi ned by the RC
constant of the blocking capacitor and R
LOAD
, assuming
R
LOAD
>> 65Ω.
Figure 8. I/Q Output Equivalent Circuit
15
16
V
CC
I
OUT
+
I
OUT
5575 F08
13
14
Q
OUT
+
Q
OUT
65 5pF656565 5pF5pF5pF
LT5575
14
5575f
APPLICATIONS INFORMATION
Care should be taken when the demodulator’s outputs are
DC-coupled to the external load to make sure that the I/Q
mixers are biased properly. If the current drain from the
outputs exceeds 6mA, there can be signifi cant degrada-
tion of the linearity performance. Each output can sink no
more than 16.8mA when the outputs are connected to an
external load with a DC voltage higher than V
CC
– 1.1V.
The I/Q output equivalent circuit is shown in Figure 8.
In order to achieve best IIP2 performance, it is important
to minimize high frequency coupling among the baseband
outputs, RF port and LO port. For a multilayer PCB layout
design, the metal lines of the baseband outputs should be
placed on the backside of the PCB as shown in Figures 2
and 3. Typically, output shunt capacitors C1-C4 are not
required for the application near 1900MHz. However, for
other frequency bands, these capacitors can be optimized
for best IIP2 performance. For example, when the oper-
ating frequency is 900MHz, the IIP2 can be improved to
54dBm or better when 10pF shunt capacitors are placed
at each output.
Enable Interface
A simplifi ed schematic of the EN pin is shown in Fig-
ure 9. The enable voltage necessary to turn on the LT5575
is 2V. To disable or turn off the chip, this voltage should
be below 1V. If the EN pin is not connected, the chip is
disabled. However, it is not recommended that the pin be
left fl oating for normal operation.
It is important that the voltage applied to the EN pin
should never exceed V
CC
by more than 0.3V. Otherwise,
the supply current may be sourced through the upper
ESD protection diode connected at the EN pin. Under no
circumstances should voltage be applied to the EN pin
before the supply voltage is applied to the V
CC
pin. If this
occurs, damage to the IC may result.
Figure 9. Enable Pin Simplifi ed Circuit
5
V
CC
EN
5575 F09
60k 60k
LT5575
LT5575
15
5575f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
UF Package
16-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1692)
4.00 ± 0.10
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.55 ± 0.20
1615
1
2
BOTTOM VIEW—EXPOSED PAD
2.15 ± 0.10
(4-SIDES)
0.75 ± 0.05
R = 0.115
TYP
0.30 ± 0.05
0.65 BSC
0.200 REF
0.00 – 0.05
(UF16) QFN 10-04
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.72 ±0.05
0.30 ±0.05
0.65 BSC
2.15 ± 0.05
(4 SIDES)
2.90 ± 0.05
4.35 ± 0.05
PACKAGE OUTLINE
PIN 1 NOTCH R = 0.20 TYP
OR 0.35 × 45° CHAMFER

LT5575EUF#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Modulator / Demodulator 800 MHz to 2.7GHz Direct I/Q Demodulator
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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