MAX6620ATI+ Datasheet MAX6620ATI+T, MAX6620ATI+ | P10-P12

MAX6620

Quad Linear Fan-Speed Controller

Maxim Integrated

Slave Address

A master initiates communication with a slave device by

issuing a START condition followed by a slave address

byte. As shown in Figure 5, the slave address byte con-

sists of 7 address bits and a read/write bit (R/W). When

idle, the MAX6620 continuously waits for a START con-

dition followed by its slave address. The first four bits

(MSBs) of the slave address have been factory pro-

grammed and are always 0101 and the seventh bit is 0.

Connect ADDR to GND or V

, or leave it unconnected

to program D2 and D1 of the slave address according

to Table 1.

After receiving the address, the MAX6620 (slave)

issues an acknowledgement by pulling SDA low for one

clock cycle.

Data Byte (Read and Write)

Single Read and Burst Read. A single read begins

with the bus master issuing a START condition followed

by the seven slave ID address bits and a zero (WR,

Figure 2), which is followed by an acknowledge bit (A)

from the slave corresponding to the slave ID. Next, the

master sends out an 8-bit register address, which is

also followed by an acknowledge bit from the slave.

The bus master issues another START condition and

the same seven slave ID address bits followed by a one

(RD, Figure 2), with the slave producing an acknowl-

edge bit. The slave then sends out the 8-bit data corre-

sponding to the register address previously written by

the master. The bus master sends back a not-acknowl-

edge bit (A). This completes the single read process

and a STOP condition is issued by the bus master.

In a burst read, the process is the same as a single

read except that the bus master issues an acknowl-

edge bit after each byte transmitted by the slave. After

each acknowledge bit, the register address increments

by one, and the data from the next register is transmit-

ted by the slave. The process continues, with data

reads followed by acknowledges. After the register with

the highest address is read, the register pointer rolls

over to point to the first register. To terminate a burst

read, the bus master issues a STOP condition.

Single Write and Burst Write. A single write begins

with the bus master issuing a START condition followed

by the seven slave ID address bits and a zero (WR,

Figure 2), which is followed by an acknowledge bit (A)

from the slave corresponding to the slave ID. Next, the

master sends out an 8-bit register address, which is

also followed by an acknowledge bit from the slave.

After the acknowledge bit, 8-bit data is written to the

A STOP condition is issued by the bus master to com-

plete the single write process.

In a burst write, the process is similar to a single write

except that the master does not issue a STOP condition

immediately after the first byte has been written. After

the first write is completed, the slave issues an

acknowledge bit, the register address increments by

one, and the data to be written to the next register is

transmitted by the master. The process continues, with

data writes followed by acknowledges. After the regis-

ter with the highest available address is written, the reg-

ister pointer rolls over to point to the first register. To

terminate a burst write, the bus master issues a STOP

condition.

Fan Drive

The MAX6620 uses external pass transistors to power

the fans. DACOUT1–DACOUT4 adjust the power-

supply voltage for each fan by driving the base of a

PNP bipolar transistor, or the gate of a p-MOSFET. The

resulting fan-supply voltage is fed back to DACFB_.

This closes the voltage feedback loop. The system

power supply for the output devices is V

FAN

. V

FAN

SLAVE ADDRESS

ADDR CONNECTION

HEX BINARY

GND 0x50 0101 000

Unconnected 0x52 0101 010

0x54 0101 100

Table 1. Slave Address Setting with

ADDR Pin

SDA

SCL

0101

1234

D2 D1 0 R/W

56789

ACKNOWLEDGE

Figure 5. MAX6620 Slave Address Byte

MAX6620

Quad Linear Fan-Speed Controller

Maxim Integrated

BIT 7…………….……………… BIT 0 ACK BIT BIT 7…………….…………………BIT ACK BIT

8-BIT DATA8-BIT REGISTER ADDRESS

8-BIT REGISTER ADDRESS

BIT 7…….…….…………BIT 0 ACK BIT

7-BIT SLAVE ID 0 AS ASS P

SINGLE WRITE

SINGLE READ

BURST WRITE

BURST READ

BIT 7…………….……….BIT 0 ACK BIT

BIT 7………….…………BIT 0 ACK BITBIT 7…………….……………BIT 0 ACK BIT

8-BIT DATA

BIT 7…….…………BIT 0 ACK BIT

7-BIT SLAVE ID

0 AS AS S 7-BIT SLAVE ID

1ASS P

FIRST 8-BIT DATA

8-BIT REGISTER ADDRESS

BIT 7…………….…………BIT 0 ACK BIT

BIT 7…………….………BIT 0 ACK BIT BIT 7…………….……………BIT 0 ACK BIT

AS7-BIT SLAVE ID 0 AS

LAST 8-BIT DATA AS PS

BIT 7……….……………BIT 0 ACK BIT

BIT 7……….…………………BIT 0 ACK BIT

LAST 8-BIT DATA

BIT 7…………….………… BIT 0 ACK BIT

7-BIT SLAVE ID

0 AS AS 7-BIT SLAVE ID 1 AS FIRST 8-BIT DATA AM

BIT 7…………….…………… BIT 0 ACK BIT

S: 2-WIRE BUS START CONDITION BY MASTER

P: 2-WIRE BUS STOP CONDITION BY MASTER

AS: ACKNOWLEDGE BY SLAVE

AM: ACKNOWLEDGE BY MASTER

AM: NO ACKNOWLEDGE BY MASTER

Figure 6. Read and Write Summary

MAX6620

Quad Linear Fan-Speed Controller

Maxim Integrated

nominally 12V or 5V. The drive to the fans is proportion-

al to V

FAN

. See the

Fan_ Target Drive Voltage Registers

and the

Applications Information

sections for more

details.

Fan-Speed Control

DAC (Voltage) Mode. In DAC mode, the MAX6620 sim-

ply sets the voltage that powers the fan. The fan’s

speed is related, but not precisely proportional to, the

drive voltage. The drive voltage is set by the Fan_

Target Drive Voltage registers and may be read from

the Fan_ Drive Voltage registers. Because the output

voltage can ramp to new values at a controlled rate, the

values in the two registers may be different. See the

and

Applications Information

sec-

tions for details.

RPM Mode. In RPM mode, the MAX6620 monitors

tachometer output pulses from the fan and adjusts the

fan drive voltage to force the fan’s speed to the desired

value. Fan speed is measured by counting the number

of internal 8192Hz clock cycles that take place during a

selectable number of tachometer periods. The number

of clock cycles counted (11-bit value) is stored in the

Fan_ TACH Count registers, and the desired number of

cycles is stored in the Fan_ Target TACH Count regis-

ters. See the

and

Applications

Information

sections for details.

Rate-of-Change Control. Sudden changes in fan

speed can be easily heard by users. The MAX6620

helps reduce the audibility of fan-speed changes by

controlling the rate at which the drive to the fan is incre-

mented. Four bits in the Fan_ Dynamics registers set

the rate at which the fan drive voltage is incremented.

This allows the time required for a change in fan speed

to be varied from 0 (in DAC mode only) to several min-

utes. See the

and

Applications

Information

sections for details.

Monitoring Tachometer Signals. The TACH_ inputs

accept tachometer or “locked-rotor” output signals from

3- or 4-wire fans. When measuring fan speed, the

MAX6620 counts the number of internal 8192Hz clock

cycles that occur during 1, 2, 4, 8, 16, or 32 tachometer

periods. The number of tachometer periods is selec-

table for each fan by using the appropriate Fan_

Dynamics register. Tachometer pulses <25µs in dura-

tion are ignored to minimize the effect of noise on the

tachometer lines.

The TACH count for a given RPM can be obtained from

the following equation:

where:

NP = number of tachometer pulses per revolution. Most

general-purpose brushless DC fans produce two

tachometer pulses per revolution.

SR = 1, 2, 4, 8, 16, or 32. See the Fan_ Speed Range

information in the

Fan_ Dynamics Register

(06h, 07h,

08h, 09h)—POR = 0100 1100

section.

The tachometer count consists of 11 bits in the Fan_

TACH Count registers and is available in RPM and DAC

modes. In RPM mode, the desired fan count is written

to the Fan_ Target TACH Count registers.

Fan Failure Detection

When enabled, the MAX6620 monitors the TACH_

inputs to determine when a fan has failed. For fans with

tachometer outputs, failure is detected in various ways

depending on the fan control mode. In every case, four

consecutive fault detections are required to decide

whether the fan has failed. In DAC mode, the Fan_

Target TACH Count registers hold the upper limit for

tachometer count values; a fault condition is identified

when a TACH count exceeds the value written to the

Fan_ Target TACH Count registers for more than 1s. In

RPM mode, a fault condition is identified when any of

the following three conditions occur for more than 1s: 1)

the TACH count exceeds the value of the Fan_ Target

TACH Count registers while the fan drive voltage is at

full-scale, 2) the TACH count exceeds two times the

Fan_ Target TACH Count value, or 3) the TACH count

reaches its full count of 7FFh.

Some fans have locked rotor outputs that produce a

logic-level output to indicate that the fan has stopped

spinning. These signals can be monitored by setting

D2:D1 in the Fan_ Configuration registers. D2 selects

locked rotor or tachometer monitoring and D1 selects the

polarity of the locked rotor signal. A fan fault has occurred

when a locked rotor signal has been present for 1s.

Fan failure is indicated in the Fan Fault register and

also with the open-drain FAN_FAIL output. The

FAN_FAIL output may be masked using the mask bits

in the Fan Fault register. When a fan failure is detected,

drive to the affected fan is removed. Drive may be

restored by writing a new DAC or fan count target to the

fan’s control registers. The global configuration regis-

TACH count

RPM

NP RPM

×× =

8192

491520

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MAX6620ATI+

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Maxim Integrated

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Motor / Motion / Ignition Controllers & Drivers Quad Linear Fan Speed Controlle

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MAX6620ATI+

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