MAX6620ATI+ Datasheet MAX6620ATI+T, MAX6620ATI+ | P7-P9

Pin Description

PIN NAME FUNCTION

1 SCL I

C Serial-Clock Input. Can be pulled up to 5.5V regardless of V

. Open circuit when V

= 0V.

2 SDA

Open-Drain, I

C Serial-Data Input/Output. Can be pulled up to 5.5V regardless of V

. Open

circuit when V

= 0V.

3 WD_START

Startup Watchdog Set Input. This input is sampled when power is first applied and sets the initial

C watchdog behavior. When connected to GND, the watchdog function is disabled. When

connected to V

, the MAX6620 monitors SDA. If 10s elapse without a valid I

C transaction, the

fan drive goes to 100%.

4, 10, 11, 18,

GND Ground

5 ADDR

C Address Set Input. This input is sampled when power is first applied and sets the I

C slave

address. When connected to GND, the slave address will be 0x50. When unconnected, the slave

address will be 0x52. When connected to V

, the slave address will be 0x54.

6 DAC_START

Startup Fan Drive DAC Set Input. This input is sampled when power is first applied and sets the

power-up value for the fan drive voltage. When connected to GND, the fan drive voltage will be

0%. When unconnected, the fan drive voltage will be 75%. When connected to V

, the fan drive

voltage will be 100%.

7S P IN U P _S TART

Startup Spin-Up Set Input. This input is sampled when power is first applied and sets the initial

spin-up behavior. When connected to GND, spin-up is disabled. When connected to V

power-up, the fan is driven with a full-scale drive voltage until two tachometer pulses have been

detected, or 1s has elapsed. When unconnected, the fan is driven with a full-scale drive voltage

until two tachometer pulses have been detected, or 0.5s has elapsed. Spin-up behavior may be

modified by writing appropriate settings to the MAX6620’s registers.

8, 9 X1, X2

Crystal Oscillator Inputs. Connections for a standard 32.768kHz quartz crystal. The internal

oscillator circuitry is designed for operation with a crystal having a specified load capacitance

) of 12pF. Connect an external 32.768kHz oscillator across X1 and X2 for operation with the

external oscillator. If no crystal or external oscillator is connected, the MAX6620 will use its

internal oscillator.

12, 17, 19, 24

DACOUT4–

DACOUT1

Fan Drive DAC Outputs. Connect to the gate of a p-channel MOSFET or base of a PNP bipolar

transistor.

13, 16, 20, 23

DACFB4–

DACFB1

D AC Feed b ack Inp uts. C onnect a 0.1µF cap aci tor b etw een these p i ns and GN D . C onnect to the

sup p l y p i n of the fan and to the d r ai n of a p - channel M O S FE T or col l ector of a P N P b i p ol ar tr ansi stor .

14, 15, 21, 22 TACH4–TACH1 Fan Tachometer Logic Inputs. These inputs accept input voltages up to V

FAN

26 FAN

Fan Power-Supply Voltage Input. Connect to the fan power supply (V

FAN

). Bypass with a 0.1µF

capacitor to GND.

27 VCC Power-Supply Input. 3.3V nominal. Bypass V

to GND with a 0.1µF capacitor.

28 FAN_FAIL

Active-Low, Open-Drain Fan Failure Output. Active only when fault is present; open-circuit when

= 0V. This pin can be pulled up to 5.5V regardless of V

—EP

Exposed Paddle. Internally connected to GND. Connect to a large ground plane to maximize

thermal performance. Not intended as an electrical connection point.

MAX6620

Quad Linear Fan-Speed Controller

Maxim Integrated

MAX6620

Quad Linear Fan-Speed Controller

Maxim Integrated

Write Byte Format

Read Byte Format

Send Byte Format

Receive Byte Format

Slave Address: equiva-

lent to chip-select line of

a 3-wire interface

Command Byte: selects which

Data Byte: data goes into the register

set by the command byte (to set

thresholds, configuration masks, and

sampling rate)

Slave Address: equiva-

lent to chip-select line

Command Byte: selects

which register you are

reading from

Slave Address: repeated

due to change in data-

flow direction

Data Byte: reads from

the register set by the

command byte

Command Byte: sends com-

mand with no data, usually

used for one-shot command

Data Byte: reads data from

the register commanded

by the last read byte or

write byte transmission;

also used for SMBus alert

response return address

S = START CONDITION SHADED = SLAVE TRANSMISSION

P = STOP CONDITION A = NOT ACKNOWLEDGED

Figure 2. I

C Protocols

S ADDRESS RD A DATA

7 bits 8 bits

WRS A COMMAND A P

8 bits

ADDRESS

7 bits

ADATA

8 bits

ACOMMAND

8 bits

AWRADDRESS

7 bits

S ADDRESS WR A COMMAND A S ADDRESS

7 bits8 bits7 bits

RD A DATA

8 bits

Detailed Description

The MAX6620 controls the speeds of up to four fans

using four independent linear voltage outputs. The

drive voltages for the fans are controlled directly over

the I

C interface. Each of the outputs (DACOUT1–

DACOUT4) drive the base of an external PNP or the

gate of a p-channel MOSFET. Voltage feedback at the

fan’s power-supply terminal is used to force the output

voltage.

The MAX6620 monitors fan tachometer logic outputs for

precise (1%) control of fan RPM and detection of fan

failure. When the MAX6620 is used with 2-wire fans,

these inputs are not used, and the fans can be driven

to the desired voltage without using tachometer feed-

back.

Three inputs set the fan drive status on application of

power. The DAC_START input selects the fan-supply

voltage (100%, 75%, or 0%) at startup to ensure appro-

priate fan drive when power is first applied. The

SPIN_START input selects whether spin-up will be

applied to the fans at power-up. WD_START selects

whether lack of I

C activity will force the fans to full

speed. When the watchdog function is enabled, the

fans will be driven to full speed if there is no I

C activity

for a period of 2s, 6s, or 10s.

Digital Interface

The MAX6620 features an I

C-compatible, 2-wire serial

interface consisting of a bidirectional serial data line

(SDA) and a serial clock line (SCL). SDA and SCL facili-

tate bidirectional communication between the MAX6620

and the master at rates up to 400kHz. The master (typi-

cally a microcontroller) initiates data transfer on the bus

and generates SCL. SDA and SCL require 4.7kΩ (typ)

pullup resistors.

Bit Transfer

One data bit is transferred during each SCL clock

cycle. Nine clock cycles are required to transfer the

data into or out of the MAX6620. The data on SDA must

remain stable during the high period of the SCL clock

pulse, as changes in SDA while SCL is high are control

signals (see the

START and STOP Conditions

section).

Both SDA and SCL idle high.

MAX6620

Quad Linear Fan-Speed Controller

Maxim Integrated

START and STOP Conditions

The master initiates a transmission with a START condi-

tion (S), a high-to-low transition on SDA with SCL high.

The master terminates a transmission with a STOP condi-

tion (P), a low-to-high transition on SDA while SCL is high

(Figure 3). The STOP condition frees the bus and places

all devices in F/S mode (Figure 1). Use a repeated

START condition (Sr) in place of a STOP condition to

leave the bus active and in its current timing mode.

Acknowledge Bits

Successful data transfers are acknowledged with an

acknowledge bit (A) or a not-acknowledge bit (A). Both

the master and the MAX6620 (slave) generate acknowl-

edge bits. To generate an acknowledge, the receiving

device must pull SDA low before the rising edge of the

acknowledge-related clock pulse (9th pulse), and keep it

low during the high period of the clock pulse (Figure 4).

To generate a not acknowledge, the receiver allows

SDA to be pulled high before the rising edge of the

acknowledge-related clock pulse, and leaves it high

during the high period of the clock pulse. Monitoring

the acknowledge bits allows for detection of unsuc-

cessful data transfers. An unsuccessful data transfer

happens if a receiving device is busy or if a system

fault has occurred. In the event of an unsuccessful data

transfer, the master should reattempt communication at

a later time.

A = START CONDITION

B = MSB OF ADDRESS CLOCKED INTO SLAVE

C = LSB OF ADDRESS CLOCKED INTO SLAVE

D = R/W BIT CLOCKED INTO SLAVE

E = SLAVE PULLS SMBDATA LINE LOW

F = ACKNOWLEDGE BIT CLOCKED INTO MASTER

G = MSB OF DATA CLOCKED INTO SLAVE

H = LSB OF DATA CLOCKED INTO SLAVE

I = MASTER PULLS DATA LINE LOW

J = ACKNOWLEDGE CLOCKED INTO SLAVE

K = ACKNOWLEDGE CLOCK PULSE

L = STOP CONDITION

M = NEW START CONDITION

SCL

AB CD

FG H

SDA

SU:STA

HD:STA

LOW

HIGH

SU:DAT

HD:DAT

SU:STO

BUF

Figure 3. I

C Write Timing Diagram

A = START CONDITION

B = MSB OF ADDRESS CLOCKED INTO SLAVE

C = LSB OF ADDRESS CLOCKED INTO SLAVE

D = R/W BIT CLOCKED INTO SLAVE

E = SLAVE PULLS SMBDATA LINE LOW

F = ACKNOWLEDGE BIT CLOCKED INTO MASTER

G = MSB OF DATA CLOCKED INTO MASTER

H = LSB OF DATA CLOCKED INTO MASTER

I = MASTER PULLS DATA LINE LOW

J = ACKNOWLEDGE CLOCKED INTO SLAVE

K = ACKNOWLEDGE CLOCK PULSE

L = STOP CONDITION

M = NEW START CONDITION

SCL

AB CD

HIJ

SDA

SU:STA

HD:STA

LOW

HIGH

SU:DAT

SU:STO

BUF

LMK

Figure 4. I

C Read Timing Diagram

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30

MAX6620ATI+

Mfr. #:

Buy MAX6620ATI+

Manufacturer:

Maxim Integrated

Description:

Motor / Motion / Ignition Controllers & Drivers Quad Linear Fan Speed Controlle

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MAX6620ATI+

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