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74LV02D,118

P1-P3P4-P6P7-P9P10-P12P13-P13
Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com (email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
- © Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and
understanding,
Kind regards,
Team Nexperia
1. General description
The 74LV02 is a low-voltage Si-gate CMOS device that is pin and function compatible with
74HC02 and 74HCT02.
The 74LV02 provides a quad 2-input NOR function.
2. Features
■ Wide operating voltage: 1.0 V to 5.5 V
■ Optimized for low voltage applications: 1.0 V to 3.6 V
■ Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
■ Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25 °C
■ Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
=25°C
■ ESD protection:
◆ HBM JESD22-A114E exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V
■ Multiple package options
■ Specified from −40 °Cto+85°C and from −40 °C to +125 °C
3. Ordering information
74LV02
Quad 2-input NOR gate
Rev. 04 — 20 December 2007 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LV02D −40 °C to +125 °C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LV02PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74LV02BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
SOT762-1
74LV02_4 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 04 — 20 December 2007 2 of 12
NXP Semiconductors
74LV02
Quad 2-input NOR gate
4. Functional diagram
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram for one gate
mna216
1A
1B
1Y
3
2
1
2A
2B
2Y
6
5
4
3A
3B
3Y
9
8
10
4A
4B
4Y
12
11
13
001aah084
2
1
3
5
4
≥1
6
≥1
8
10
≥1
9
11
13
≥1
12
mna215
A
B
Y
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14
02
1Y V
CC
1A 4Y
1B 4B
2Y 4A
2A 3Y
2B 3B
GND 3A
001aac919
1
2
3
4
5
6
7
8
10
9
12
11
14
13
001aah093
74LV02
Transparent top view
V
CC
(1)
2B 3B
2A 3Y
2Y 4A
1B 4B
1A 4Y
GND
3A
1Y
V
CC
6 9
5 10
4 11
3 12
2 13
7
8
1
14
terminal 1
index area
Table 2. Pin description
Symbol Pin Description
1Y 1 data output
1A 2 data input
1B 3 data input
P1-P3P4-P6P7-P9P10-P12P13-P13

74LV02D,118

Mfr. #:
Buy 74LV02D,118
Manufacturer:
Nexperia
Description:
Logic Gates QUAD 2-INPUT NOR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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