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74LV02D,118

P1-P3P4-P6P7-P9P10-P12P13-P13
74LV02_4 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 04 — 20 December 2007 6 of 12
NXP Semiconductors
74LV02
Quad 2-input NOR gate
11. Waveforms
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 6. The input (nA, nB) to output (nY) propagation delays
001aah085
t
PHL
t
PLH
V
M
V
M
nY output
nA, nB input
V
I
GND
V
OH
V
OL
Table 8. Measurement points
Supply voltage Input Output
V
CC
V
M
V
M
< 2.7 V 0.5V
CC
0.5V
CC
2.7 V to 3.6 V 1.5 V 1.5 V
≥ 4.5 V 0.5V
CC
0.5V
CC
Test data is given in Table 9.
Definitions test circuit:
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
Fig 7. Load circuit for switching times
V
CC
V
I
V
O
001aaa663
D.U.T.
C
L
50 pF
R
T
R
L
1 kΩ
PULSE
GENERATOR
Table 9. Test data
Supply voltage Input
V
CC
V
I
t
r
, t
f
< 2.7 V V
CC
≤ 2.5 ns
2.7 V to 3.6 V 2.7 V ≤ 2.5 ns
≥ 4.5 V V
CC
≤ 2.5 ns
74LV02_4 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 04 — 20 December 2007 7 of 12
NXP Semiconductors
74LV02
Quad 2-input NOR gate
12. Package outline
Fig 8. Package outline SOT108-1 (SO14)
UNIT
A
max.
A
1
A
2
A
3
b
p
cD
(1)
E
(1)
(1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
0.7
0.6
0.7
0.3
8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
w M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v M
A
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.35
0.34
0.16
0.15
0.05
1.05
0.041
0.244
0.228
0.028
0.024
0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
74LV02_4 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 04 — 20 December 2007 8 of 12
NXP Semiconductors
74LV02
Quad 2-input NOR gate
Fig 9. Package outline SOT402-1 (TSSOP14)
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(2) (1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
0.4
0.3
0.72
0.38
8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153
99-12-27
03-02-18
w M
b
p
D
Z
e
0.25
17
14
8
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v M
A
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
A
max.
1.1
pin 1 index
P1-P3P4-P6P7-P9P10-P12P13-P13

74LV02D,118

Mfr. #:
Buy 74LV02D,118
Manufacturer:
Nexperia
Description:
Logic Gates QUAD 2-INPUT NOR
Lifecycle:
New from this manufacturer.
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