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EP9307-CRZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50
DS667F2 Copyright 2010 Cirrus Logic (All Rights Reserved) 13
EP9307
ARM9 SOC with Ethernet, USB, Display and Touchscreen
DC Characteristics
Note: 3. For open drain pins, high level output voltage is dependent on the external load.
4. All inputs that do not include internal pull-ups or pull-downs, must be externally driven for proper operation (See Table S on
page 46). If an input is not driven, it should be tied to power or ground, depending on the particular function. If an I/O pin is not
driven and programmed as an input, it should be tied to power or ground through its own resistor.
(T
A
= 0 to 70° C; CVDD = VDD_PLL = 1.8; RVDD = 3.3 V;
All grounds = 0 V; all voltages with respect to 0 V unless otherwise noted)
Parameter Symbol Min Max Unit
High level output voltage Iout = -4 mA (Note 3)
V
oh
0.85 × RVDD - V
Low level output voltage Iout = 4 mA
V
ol
-0.15 × RVDD V
High level input voltage (Note 4)
V
ih
0.65 × RVDD VDD + 0.3 V
Low level input voltage (Note 4)
V
il
−0.3 0.35 × RVDD V
High level leakage current Vin = 3.3 V (Note 4)
I
ih
-10µA
Low level leakage current Vin = 0 (Note 4)
I
il
--10µA
Parameter Min Typ Max Unit
Power Supply Pins (Outputs Unloaded)
Power Supply Current: CVDD/VDD_PLL Total
RVDD
-
-
190
45
240
80
mA
mA
Low-Power Mode Supply Current CVDD/VDD_PLL Total
RVDD
-
-
2
1.0
3.5
2
mA
mA
14 Copyright 2010 Cirrus Logic (All Rights Reserved) DS667F2
EP9307
ARM9 SOC with Ethernet, USB, Display and Touchscreen
Timings
Timing Diagram Conventions
This data sheet contains one or more timing diagrams. The following key explains the components used in these
diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached
unless specifically stated.
Figure 1. Timing Diagram Drawing Key
Timing Conditions
Unless specified otherwise, the following conditions are true for all timing measurements.
•T
A
= 0 to 70° C
• CVDD = VDD_PLL = 1.8V
•RVDD = 3.3V
• All grounds = 0 V
• Logic 0 = 0 V, Logic 1 = 3.3 V
• Output loading = 50 pF
• Timing reference levels = 1.5 V
• The Processor Bus Clock (HCLK) is programmable and is set by the user. The frequency is typically between
33 MHz and 100 MHz (92 MHz for industrial conditions).
Clock
High to Low
High/Low to High
Bus Change
Bus Valid
Undefined/Invalid
Valid Bus to Tristate
Bus/Signal Omission
DS667F2 Copyright 2010 Cirrus Logic (All Rights Reserved) 15
EP9307
ARM9 SOC with Ethernet, USB, Display and Touchscreen
Memory Interface
SDRAM Load Mode Register Cycle
Figure 2 through Figure 5 define the timings associated with all phases of the SDRAM. The following table contains the
values for the timings of each of the SDRAM modes.
Parameter Symbol Min Typ Max Unit
SDCLK high time
t
clk_high
-
(t
HCLK
) / 2
-ns
SDCLK low time
t
clk_low
-
(t
HCLK
) / 2
-ns
SDCLK rise/fall time
t
clkrf
-24ns
Signal delay from SDCLK rising edge time
t
d
--8ns
Signal hold from SDCLK rising edge time
t
h
1--ns
DQMn delay from SDCLK rising edge time
t
DQd
--8ns
DQMn hold from SDCLK rising edge time
t
DQh
1--ns
DA valid setup to SDCLK rising edge time
t
DAs
2--ns
DA valid hold from SDCLK rising edge time
t
DAh
3--ns
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement
SDCLK
SDCSn
RASn
CASn
SDWEn
DQMn
AD
DA
OP-Code
t
clk_high
t
clk_low
t
clkrf
t
d
t
h
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EP9307-CRZ

Mfr. #:
Buy EP9307-CRZ
Manufacturer:
Cirrus Logic
Description:
Microprocessors - MPU IC Universl Pltform ARM9 SOC Prcessor
Lifecycle:
New from this manufacturer.
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