DS667F2 Copyright 2010 Cirrus Logic (All Rights Reserved) 43
EP9307
ARM9 SOC with Ethernet, USB, Display and Touchscreen
Pin List
The following Thin-profile Fine-pitch Ball Grid Array (TFBGA) ball assignment table is sorted in order of ball.
Ball Signal Ball Signal Ball Signal Ball Signal
A1 CSn[1] E1 SDCSn[2] J10 gndc P1 SPCLK
A2 CSn[7]
E2 SDWEN J12 vddc P2 P[10]
A3 SDCLKEN
E3 DA[22] J13 vddr P3 P[11]
A4 DA[31]
E4 AD[3] J14 COL[5] P4 P[3]
A5 DA[29]
E5 DA[15] J15 COL[6] P5 AD[15]
A6 DA[27]
E6 AD[21] J16 CSn[0] P6 AD[13]
A7 HGPIO[2]
E7 DA[17] J17 COL[3] P7 AD[12]
A8 RDn
E8 vddr K1 AD[4] P8 DA[2]
A9 MIIRXD[3]
E9 vddr K2 DA[12] P9 AD[8]
A10 RXDVAL
E10 vddr K3 DA[10] P10 TCK
A11 MIITXD[1]
E11 MIIRXD[0] K4 DA[11] P11 BOOT[1]
A12 CRS
E12 TXERR K5 vddr P12 EEDAT
A13 FGPIO[7]
E13 EGPIO[2] K6 gndr P13 GRLED
A14 FGPIO[0]
E14 EGPIO[4] K8 gndc P14 RDLED
A15 WAITn
E15 EGPIO[3] K9 gndc P15 GGPIO[2]
A16 USBm[2]
E16 sXp K10 gndc P16 RXD[1]
A17 ASDI
E17 sXm K12 vddc P17 RXD[2]
B1 AD[25]
F1 RASn K13 COL[4] R1 P[9]
B2 CSn[2]
F2 SDCSn[1] K14 PLL_VDD R2 HSYNC
B3 CSn[6]
F3 SDCSn[0] K15 COL[2] R3 P[6]
B4 AD[20]
F4 DQMn[3] K16 COL[1] R4 P[5]
B5 DA[30]
F5 AD[5] K17 COL[0] R5 P[0]
B6 AD[18]
F6 gndr L1 DA[9] R6 AD[14]
B7 HGPIO[3]
F7 gndr L2 AD[2] R7 DA[4]
B8 AD[17]
F8 gndr L3 AD[1] R8 DA[1]
B9 RXCLK
F9 vddc L4 DA[8] R9 DTRn
B10 MIIRXD[1]
F10 vddc L5 BLANK R10 TDI
B11 MIITXD[2]
F11 gndr L6 gndr R11 BOOT[0]
B12 TXEN
F12 EGPIO[7] L12 gndr R12 ASYNC
B13 FGPIO[5]
F13 EGPIO[5] L13 ROW[7] R13 SSPTX[1]
B14 EGPIO[15]
F14 ADC_GND L14 ROW[5] R14 PWMOUT
B15 USBp[2]
F15 EGPIO[6] L15 PLL_GND R15 USBm[0]
B16 ARSTn
F16 sYm L16 XTALI R16 ABITCLK
B17 ADC_VDD
F17 sYp L17 XTALO R17 USBp[0]
C1 AD[23]
G1 DQMn[0] M1 BRIGHT T1 NC
C2 DA[26]
G2 CASn M2 AD[0] T2 NC
C3 CSn[3]
G3 DA[21] M3 DQMn[1] T3 V_CSYNC
C4 DA[25]
G4 AD[22] M4 DQMn[2] T4 P[7]
C5 AD[24]
G5 vddr M5 P[17] T5 P[2]
C6 AD[19]
G6 gndr M6 gndr T6 DA[7]
C7 HGPIO[5]
G12 gndr M7 gndr T7 AD[11]
C8 WRn
G13 EGPIO[9] M8 vddc T8 AD[9]
