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CY7C131-25JC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
CY7C130/CY7C131
CY7C140/CY7C141
4
AC Test Loads and Waveforms
Switching Characteristics Over the Operating Range
[6,11]
7C131-15
[3,4]
7C141-15
7C130-25
[3]
7C131-25
7C140-25
7C141-25
7C130-30
7C131-30
7C140-30
7C141-30
Parameter Description
Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
RC
Read Cycle Time 15 25 30 ns
t
AA
Address to Data Valid
[12]
15 25 30 ns
t
OHA
Data Hold from Address Change 0 00ns
t
ACE
CE LOW to Data Valid
[12]
15 25 30 ns
t
DOE
OE LOW to Data Valid
[12]
10 15 20 ns
t
LZOE
OE LOW to Low Z
[9,13, 14]
3 33ns
t
HZOE
OE HIGH to High Z
[9,13, 14]
10 15 15 ns
t
LZCE
CE LOW to Low Z
[9,13, 14]
3 55ns
t
HZCE
CE HIGH to High Z
[9,13, 14]
10 15 15 ns
t
PU
CE LOW to Power-Up
[9]
0 00ns
t
PD
CE HIGH to Power-Down
[9]
15 25 25 ns
WRITE CYCLE
[15]
t
WC
Write Cycle Time 15 25 30 ns
t
SCE
CE LOW to Write End 12 20 25 ns
t
AW
Address Set-Up to Write End 12 20 25 ns
t
HA
Address Hold from Write End 2 22ns
t
SA
Address Set-Up to Write Start 0 00ns
t
PWE
R/W Pulse Width 12 15 25 ns
t
SD
Data Set-Up to Write End 10 15 15 ns
t
HD
Data Hold from Write End 0 00ns
t
HZWE
R/W LOW to High Z
[14]
10 15 15 ns
t
LZWE
R/W HIGH to Low Z
[14]
0 00ns
Notes:
11. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
I
OL
/I
OH,
and 30-pF load capacitance.
12. AC Test Conditions use V
OH
= 1.6V and V
OL
= 1.4V.
13. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
14. t
LZCE
, t
LZWE
, t
HZOE
, t
LZOE
, t
HZCE
and t
HZWE
are tested with C
L
= 5pF as in part (b) of AC Test Loads
.
Transition is measured ±500 mV from steady state voltage.
15. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can terminate
a write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write
3.0V
5V
OUTPUT
R1 893Ω
R2
347Ω
30 pF
INCLUDING
JIGAND
SCOPE
GND
90%
90%
10%
≤ 5ns
≤5
ns
5V
OUTPUT
R1 893Ω
R2
347Ω
5pF
INCLUDING
JIGAND
SCOPE
(a)
(b)
OUTPUT 1.40V
Equivalent to:
THÉVENIN EQUIVALENT
5
V
281Ω
30
pF
BUSY
OR
INT
BUSY Output Load
(CY7C130/CY7C131 ONLY)
10%
C130-5
C130-6
ALL INPUT PULSES
250Ω
CY7C130/CY7C131
CY7C140/CY7C141
5
BUSY/INTERRUPT TIMING
t
BLA
BUSY LOW from Address Match 15 20 20 ns
t
BHA
BUSY HIGH from Address Mismatch
[16]
15 20 20 ns
t
BLC
BUSY LOW from CE LOW 15 20 20 ns
t
BHC
BUSY HIGH from CE HIGH
[16]
15 20 20 ns
t
PS
Port Set Up for Priority 5 55ns
t
WB
[17]
R/W LOW after BUSY LOW 0 00ns
t
WH
R/W HIGH after BUSY HIGH 13 20 30 ns
t
BDD
BUSY HIGH to Valid Data 15 25 30 ns
t
DDD
Write Data Valid to Read Data Valid Note
18
Note
18
Note
18
ns
t
WDD
Write Pulse to Data Delay Note
18
Note
18
Note
18
ns
INTERRUPT TIMING
t
WINS
R/W to INTERRUPT Set Time 15 25 25 ns
t
EINS
CE to INTERRUPT Set Time 15 25 25 ns
t
INS
Address to INTERRUPT Set Time 15 25 25 ns
t
OINR
OE to INTERRUPT Reset Time
[16]
15 25 25 ns
t
EINR
CE to INTERRUPT Reset Time
[16]
15 25 25 ns
t
INR
Address to INTERRUPT Reset Time
[16]
15 25 25 ns
Notes:
16. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
17. CY7C140/CY7C141 only.
18. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY
on Port B goes HIGH.
Port B’s address is toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
Switching Characteristics Over the Operating Range
[6,11]
7C130-35
7C131-35
7C140-35
7C141-35
7C130-45
7C131-45
7C140-45
7C141-45
7C130-55
7C131-55
7C140-55
7C141-55
Parameter Description Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
RC
Read Cycle Time 35 45 55 ns
t
AA
Address to Data Valid
[12]
35 45 55 ns
t
OHA
Data Hold from Address Change 0 0 0 ns
t
ACE
CE LOW to Data Valid
[12]
35 45 55 ns
t
DOE
OE LOW to Data Valid
[12]
20 25 25 ns
t
LZOE
OE LOW to Low Z
[9,13, 14]
333ns
t
HZOE
OE HIGH to High Z
[9,13, 14]
20 20 25 ns
t
LZCE
CE LOW to Low Z
[9,13, 14]
555ns
t
HZCE
CE HIGH to High Z
[9,13, 14]
20 20 25 ns
t
PU
CE LOW to Power-Up
[9]
000ns
t
PD
CE HIGH to Power-Down
[9]
35 35 35 ns
Switching Characteristics Over the Operating Range
[6,11]
(continued)
7C131-15
[3,4]
7C141-15
7C130-25
[3]
7C131-25
7C140-25
7C141-25
7C130-30
7C131-30
7C140-30
7C141-30
Parameter Description
Min. Max. Min. Max. Min. Max. Unit
CY7C130/CY7C131
CY7C140/CY7C141
6
WRITE CYCLE
[15]
t
WC
Write Cycle Time 35 45 55 ns
t
SCE
CE LOW to Write End 30 35 40 ns
t
AW
Address Set-Up to Write End 30 35 40 ns
t
HA
Address Hold from Write End 2 2 2 ns
t
SA
Address Set-Up to Write Start 0 0 0 ns
t
PWE
R/W Pulse Width 25 30 30 ns
t
SD
Data Set-Up to Write End 15 20 20 ns
t
HD
Data Hold from Write End 0 0 0 ns
t
HZWE
R/W LOW to High Z
[14]
20 20 25 ns
t
LZWE
R/W HIGH to Low Z
[14]
000ns
BUSY/INTERRUPT TIMING
t
BLA
BUSY LOW from Address Match 20 25 30 ns
t
BHA
BUSY HIGH from Address Mismatch
[16]
20 25 30 ns
t
BLC
BUSY LOW from CE LOW 20 25 30 ns
t
BHC
BUSY HIGH from CE HIGH
[16]
20 25 30 ns
t
PS
Port Set Up for Priority 5 5 5 ns
t
WB
[17]
R/W LOW after BUSY LOW 0 0 0 ns
t
WH
R/W HIGH after BUSY HIGH 30 35 35 ns
t
BDD
BUSY HIGH to Valid Data 35 45 45 ns
t
DDD
Write Data Valid to Read Data Valid Note
18
Note
18
Note
18
ns
t
WDD
Write Pulse to Data Delay Note
18
Note
18
Note
18
ns
INTERRUPT TIMING
t
WINS
R/W to INTERRUPT Set Time 25 35 45 ns
t
EINS
CE to INTERRUPT Set Time 25 35 45 ns
t
INS
Address to INTERRUPT Set Time 25 35 45 ns
t
OINR
OE to INTERRUPT Reset Time
[16]
25 35 45 ns
t
EINR
CE to INTERRUPT Reset Time
[16]
25 35 45 ns
t
INR
Address to INTERRUPT Reset Time
[16]
25 35 45 ns
Switching Characteristics Over the Operating Range
[6,11]
(continued)
7C130-35
7C131-35
7C140-35
7C141-35
7C130-45
7C131-45
7C140-45
7C141-45
7C130-55
7C131-55
7C140-55
7C141-55
Parameter Description Min. Max. Min. Max. Min. Max. Unit
Switching Waveforms
Notes:
19. R/W
is HIGH for read cycle.
20. Device is continuously selected, CE = V
IL
and OE =
V
IL
.
Read Cycle No.1
t
RC
t
AA
t
OHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
C130-7
Either Port Address Access
[19, 20]
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

CY7C131-25JC

Mfr. #:
Buy CY7C131-25JC
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 8K PARALLEL 52PLCC
Lifecycle:
New from this manufacturer.
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