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CY7C131-25JC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
CY7C130/CY7C131
CY7C140/CY7C141
7
Notes:
21. Address valid prior to or coincident with CE
transition LOW.
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
PWE
or t
HZWE
+ t
SD
to allow the data I/O pins to enter high impedance and for data
to be placed on the bus for the required t
SD
.
Switching Waveforms (continued)
t
ACE
t
LZOE
t
DOE
t
HZOE
t
HZCE
DATA VALID
DATA OUT
CE
OE
t
LZCE
t
PU
I
CC
I
SB
t
PD
Read Cycle No. 2
t
BHA
t
BDD
VALID
t
DDD
t
WDD
ADDRESS MATCH
ADDRESS MATCH
R/W
R
ADDRESS
R
D
INR
ADDRESS
L
BUSY
L
DOUT
L
Read Cycle No.3
Write Cycle No.1 (OE Three-States Data I/Os - Either Port)
t
AW
t
WC
DATA VALID
HIGH IMPEDANCE
t
SCE
t
SA
t
PWE
t
HD
t
SD
t
HA
CE
R/W
ADDRESS
t
HZOE
OE
D
OUT
DATA
IN
Either Port CE/OE Access
Either Port
C130-8
C130-9
C130-10
t
PS
t
BLA
Read with BUSY, Master: CY7C130 and CY7C131
t
RC
t
PWE
VALID
t
HD
[19, 21]
[20]
[15, 22]
CY7C130/CY7C131
CY7C140/CY7C141
8
Note:
23. If the CE
LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state
Switching Waveforms (continued)
Write Cycle No. 2 (R/W Three-States Data I/Os - Either Port)
t
AW
t
WC
t
SCE
t
SA
t
PWE
t
HD
t
SD
t
HZWE
Either Port
t
HA
HIGH IMPEDANCE
ADDRESS MATCH
t
PS
Busy Timing Diagram No. 1 (CE Arbitration)
CE
L
Valid First:
t
BLC
t
BHC
ADDRESS MATCH
t
PS
t
BLC
t
BHC
CE
R
Valid First:
DATA VALID
t
LZWE
C130-11
C130-12
C130-13
ADDRESS
CE
R/W
DATA
OUT
DATA
IN
ADDRESS
L,R
BUSY
R
CE
L
CE
R
BUSY
L
CE
R
CE
L
ADDRESS
L,R
[16, 23]
CY7C130/CY7C131
CY7C140/CY7C141
9
Switching Waveforms (continued)
Busy Timing Diagram No. 2 (Address Arbitration)
Left Address Valid First:
ADDRESS MATCH
t
PS
ADDRESS
L
BUSY
R
ADDRESS MISMATCH
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
ADDRESS MATCH ADDRESS MISMATCH
t
PS
ADDRESS
L
BUSY
L
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
Right Address Valid First:
t
PWE
t
WB
t
WH
Busy Timing Diagram No. 3
Write with BUSY (Slave:CY7C140/CY7C141)
C130-14
C130-15
C130-16
BUSY
R/W
CE
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

CY7C131-25JC

Mfr. #:
Buy CY7C131-25JC
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 8K PARALLEL 52PLCC
Lifecycle:
New from this manufacturer.
Delivery:
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