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MAX4360EAX+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
MAX4359/MAX4360/MAX4456
Low-Cost 4x4, 8x4, 8x8
Video Crosspoint Switches
4 _______________________________________________________________________________________
Pin Description
2 2 2
Parallel Data Bit D0 when SER/PAR = GND. Serial
input when SER/PAR = V
CC
.
3, 5 3, 5 3, 5 Output Buffer Address Lines
4, 6, 8, 10 4, 6, 8, 10
4, 6, 8, 10,
12, 14, 16,
18
Video Input Lines
7 7 7
Asynchronous Control Line. When LOAD = V
CC
, all the
400Ω internal active loads are on. When LOAD = GND,
external 400Ω loads must be used. The buffers must
have a resistive load to maintain stability.
9 9 9
Digital Ground. DGND pins must have the same
potential and be bypassed to AGND. DGND should
be within ±0.3V of AGND.
11 11 11
When this control line is high, the 2nd-rank registers
are loaded with the rising edge of LATCH. If this con-
trol line is low, the 2nd-rank registers are transparent
when LATCH is low, passing data directly from the
1st-rank registers to the decoders.
—
12–16, 18,
22–26
22–26 No connection. Not internally connected.
12 17 17
Connect to V
CC
for serial mode; connect to GND for
parallel mode.
13 19, 30 19, 30
Negative Supply. All V- pins must be connected to each
other and bypassed to GND separately (Figure 2).
14 20 20
In serial mode, WR (write) shifts data into the input regis-
ter. In parallel mode, WR loads data into the 1st-rank
registers. Data is latched on the rising edge.
1 21 1 1
Parallel Data Bit D1 when SER/PAR = GND. Serial out-
put for cascading multiple parts when SER/PAR = V
CC
.
D1/
SER OUT
2 3
3, 4, 6 4, 5, 7
5, 7, 9, 11,
13, 15, 17,
19
6, 8, 10, 13,
15, 17, 19,
21
8 9
10, 12 11, 14
14 16
—
1, 12, 23,
34
18 20
20, 34 22, 38
21 24
D0/SER IN
A_
IN_
LOAD
DGND
EDGE/
LEVEL
N.C.
SER/PAR
V-
WR
MAX4360 MAX4456MAX4359
DIP PLCCSO SSOP SSOP
FUNCTIONNAME
PIN
15 21 21
If EDGE/LEVEL = V
CC
, data is loaded from the 1st-
rank registers to the 2nd-rank registers on the rising
edge of LATCH. If EDGE/LEVEL = GND, data is
loaded while LATCH = GND. In addition, data is
loaded during the execution of parallel-mode func-
tions 1011 through 1110, or if LATCH = V
CC
during
the execution of the parallel-mode “software-latch”
command (1111).
22 25 LATCH
MAX4359/MAX4360/MAX4456
Low-Cost 4x4, 8x4, 8x8
Video Crosspoint Switches
_______________________________________________________________________________________ 5
Pin Description (continued)
V+
D2
D3
AGND
OUT_
CE
CE
18, 29, 4416, 26, 40
4238
4036
31, 33, 3628, 30, 32
28, 30, 32,
35, 37, 39,
41, 43
25, 27, 29,
31, 33, 35,
37, 39
2724
2623
Positive Supply. All V+ pins must be connected to each
other and bypassed to AGND separately (Figure 2).
13, 363624
Parallel Data Bit D2 when SER/PAR = GND. Not used
when SER/PAR = V
CC
.
343422
Parallel Data Bit when SER/PAR = GND. When
D3 = GND, D0–D2 specify the input channel to be con-
nected to specified buffer. When D3 = V
CC
, D0–D2
specify control codes. D3 is not used in serial mode
(SER/PAR = V
CC
).
323220
Analog Ground. AGND must be at 0.0V, since the gain-
setting resistors of the buffers are connected to these
pins.
15, 292918
Buffer Outputs. Buffer inputs are internally grounded with
a 1000 or 1001 command from the D3–D0 lines.
28, 31, 33,
35
28, 31, 33,
35
17, 19, 21,
23
Active-High Chip Enable. WR is enabled when
CE = GND and CE = V
CC
. WR is disabled when
CE = V
CC
and CE = GND.
272716
Active-Low Chip Enable. WR is enabled when
CE = GND and CE = V
CC
. WR is disabled when
CE = V
CC
and CE = GND.
———
PLCCDIPSSOPSSOPSO
NAME
PIN
FUNCTION
MAX4456MAX4360MAX4359
MAX4359/MAX4360/MAX4456
Low-Cost 4x4, 8x4, 8x8
Video Crosspoint Switches
6 _______________________________________________________________________________________
Detailed Description
Output Buffers
The MAX4456 video crosspoint switch consists of 64
T-switches in an 8x8 grid (Figure 1). The eight matrix
outputs are followed by eight wideband buffers opti-
mized for driving 400Ω and 20pF loads. The
MAX4359’s core is a 4x4 switch matrix with each of its
outputs followed by a wideband buffer. The MAX4360
has an 8x4 matrix and four output buffers. Each buffer
has an internal active load on the output that can be
readily shut off through the LOAD input (off when LOAD
= 0V). The shut-off is useful when two or more cross-
points are connected in parallel to create more input
channels. With more input channels, only one set of
buffers can be active and only one set of loads can be
driven. When active, the buffer must have either 1) an
internal load, 2) the internal load of another buffer in
another MAX4359/MAX4360/MAX4456, or 3) an exter-
nal load.
Each output can be disabled under logic control. When
a buffer is disabled, its output enters a high-impedance
state. In multichip parallel applications, the disable
function prevents inactive outputs from loading lines
driven by other devices. Disabling the inactive buffers
reduces power consumption.
The outputs connect easily to MAX4395 quad, opera-
tional amplifiers when back-terminated 75Ω coaxial
cable must be driven.
A = +1
IN0
IN1 IN2 IN3
IN4 IN5
IN6 IN7
OUTPUT
BUFFERS
OUT0
400Ω
LOAD
LATCH
EDGE/LEVEL
2nd-RANK REGISTERS
1st-RANK REGISTERS
WR
CE
CE
A0
A1
A2
D3
D2
V+
V-
AGND
DGND
D1/SER OUT
D0/SER IN
SER/PAR
MAX4456
8x8
SWITCH
MATRIX
A = +1
OUT7
400Ω
Figure 1. MAX4456 Functional Diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

MAX4360EAX+T

Mfr. #:
Buy MAX4360EAX+T
Manufacturer:
Maxim Integrated
Description:
Analog & Digital Crosspoint ICs 8x4 Video Crosspoint Switch
Lifecycle:
New from this manufacturer.
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