CY62256EV18LL-70SNXIT

CY62256EV18 MoBL
®
Document Number: 001-69650 Rev. *D Page 4 of 15
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Supply voltage to ground
potential .......................................................–0.2 V to 2.45 V
DC voltage applied to outputs
in high Z State
[2, 3]
......................................–0.2 V to 2.45 V
DC input voltage
[2, 3]
...................................–0.2 V to 2.45 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(MIL-STD-883, method 3015) ................................ > 2001 V
Latch-up current .................................................... > 200 mA
Operating Range
Device Range
Ambient
Temperature
V
CC
[4]
CY62256EV18LL Industrial –40 °C to +85 °C 1.65 V to
2.25 V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
70 ns
Unit
Min Typ
[5]
Max
V
OH
Output HIGH voltage I
OH
= –0.1 mA 1.4 V
V
OL
Output LOW voltage I
OL
= 0.1 mA 0.2 V
V
IH
Input HIGH voltage V
CC
= 1.65 V to 2.25 V 1.4 V
CC
+ 0.2 V V
V
IL
Input LOW voltage V
CC
= 1.65 V to 2.25 V –0.2 0.4 V
I
IX
Input leakage current GND < V
I
< V
CC
–1 +1 µA
I
OZ
Output leakage current GND < V
O
< V
CC
, output disabled –1 +1 µA
I
CC
V
CC
operating supply current f = f
max
= 1/t
RC
V
CC
= 2.25 V
I
OUT
= 0 mA
CMOS levels
–1116mA
f = 1 MHz 1.3 2.0 mA
I
SB1
Automatic CE power-down
current — CMOS inputs
CE > V
CC
0.2 V,
V
IN
> V
CC
– 0.2 V, V
IN
< 0.2 V
f = f
max
(address and data only),
f = 0 (OE
and WE), V
CC
= 2.25 V
–14µA
I
SB2
[6]
Automatic CE power-down
current — CMOS inputs
CE > V
CC
– 0.2 V,
V
IN
> V
CC
– 0.2 V or V
IN
< 0.2 V,
f = 0, V
CC
= 2.25 V
–14µA
Notes
2. V
IL(min)
= –2.0 V for pulse durations less than 20 ns.
3. V
IH(max)
= V
CC
+ 0.5 V for pulse durations less than 20 ns.
4. Full device AC operation assumes a 100
µs ramp time from 0 to V
CC(min)
and 200 µs wait time after V
CC
stabilization.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
6. Chip enables (CE
) must be at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
CY62256EV18 MoBL
®
Document Number: 001-69650 Rev. *D Page 5 of 15
Capacitance
Parameter
[7]
Description Test Conditions Max Unit
C
IN
Input capacitance T
A
= 25 °C, f = 1 MHz, V
CC
= V
CC(typ)
10 pF
C
OUT
Output capacitance 10 pF
Thermal Resistance
Parameter
[7]
Description Test Conditions 28-pin SOIC Unit
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit
board
76.56 °C/W
JC
Thermal resistance
(junction to case)
36.07 °C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
V
CC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT V
TH
Equivalent to: THEVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Parameters 1.8 V Unit
R1 13500
R2 10800
R
TH
6000
V
TH
0.8 V
CY62256EV18 MoBL
®
Document Number: 001-69650 Rev. *D Page 6 of 15
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ
[8]
Max Unit
V
DR
V
CC
for data retention 1.0 V
I
CCDR
[9]
Data retention current V
CC
= 1.0 V, CE > V
CC
 0.2 V,
V
IN
> V
CC
0.2 V or V
IN
< 0.2 V
––3µA
t
CDR
[10]
Chip deselect to data retention
time
0––ns
t
R
[11]
Operation recovery time 70 ns
Data Retention Waveform
Figure 3. Data Retention Waveform
[12]
V
CC(min)
V
CC(min)
t
CDR
V
DR
> 1.0 V
DATA RETENTION MODE
t
R
V
CC
CE
Notes
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
9. Chip enables (CE
) must be at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
10. Tested initially and after any design or process changes that may affect these parameters.
11. Full device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 µs or stable at V
CC(min)
100 µs.
12. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.

CY62256EV18LL-70SNXIT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
SRAM 256Kb 1.8V 70ns 32K x 8 LP SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet