Document Number: 001-69650 Rev. *D Page 7 of 15
Switching Characteristics
Over the Operating Range
Parameter
[13]
Description
70 ns
Unit
Min Max
Read Cycle
t
RC
Read cycle time 70 – ns
t
AA
Address to data valid – 70 ns
t
OHA
Data hold from address change 5 – ns
t
ACE
CE LOW to data valid – 70 ns
t
DOE
OE LOW to data valid – 35 ns
t
LZOE
OE LOW to low Z
[14]
5 – ns
t
HZOE
OE HIGH to high Z
[14, 15]
– 25 ns
t
LZCE
CE
LOW to low Z
[14]
5
–
ns
t
HZCE
CE HIGH to high Z
[14, 15]
– 25 ns
t
PU
CE LOW to power-up
0
–
ns
t
PD
CE HIGH to power-down – 70 ns
Write Cycle
[16, 17]
t
WC
Write cycle time 70 – ns
t
SCE
CE LOW to write end 60 – ns
t
AW
Address setup to write end 60 – ns
t
HA
Address hold from write end 0 – ns
t
SA
Address setup to write start 0 – ns
t
PWE
WE pulse width
50
–
ns
t
SD
Data setup to write end 30 – ns
t
HD
Data hold from write end 0 – ns
t
HZWE
WE LOW to high Z
[14, 15]
– 25 ns
t
LZWE
WE HIGH to low Z
[14]
5 – ns
Notes
13. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
CC(typ)
/2, input
pulse levels of 0 to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
as shown in the Figure 2 on page 5.
14. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
15. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the output enter a high impedance state.
16. The internal write time of the memory is defined by the overlap of WE
, CE = V
IL
. All signals must be ACTIVE to initiate a write and any of these signals can terminate
a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
17. The minimum write cycle pulse width for Write Cycle No. 3 (WE
Controlled, OE low) should be equal to the sum of t
SD
and t
HZWE
.
