13
LTC1147-3.3
LTC1147-5/LTC1147L
sn1147 1147fds
APPLICATIO S I FOR ATIO
WUU
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Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1147 series. These items are also illustrated graphi-
cally in the layout diagram of Figure 7. Check the following
in your layout:
1. Are the signal and power grounds segregated? The
LTC1147 ground (Pin 7) must return separately to a)
the power and b) signal grounds.
The power ground
(a) returns to the source anode of the Schottky diode
and (–) plate of C
IN
, which should have lead lengths
as short as possible. The signal ground (b) connects
to the (–) plate of C
OUT
.
2. Does the LTC1147 SENSE
–
(Pin 4) connect to a point
close to R
SENSE
and the (+) plate of C
OUT
?
3. Are the SENSE
–
and SENSE
+
leads routed together with
minimum PC trace spacing? The 1000pF capacitor
between Pins 4 and 5 should be as close as possible to
the LTC1147.
4. Does the (+) plate of C
IN
connect to the source of the
P-channel MOSFET as closely as possible? This capaci-
tor provides the AC current to the P-channel MOSFET.
5. Is the input
decoupling capacitor (0.1µF/1µF) con-
nected closely between V
IN
(Pin 1) and ground (Pin 7)?
This capacitor carries the MOSFET driver peak currents.
6. On fixed output versions, is the SHDN (Pin 6) actively
pulled to ground during normal operation? The SHDN
pin is high impedance and must not be allowed to float.
For additional High Efficiency application circuits see Application Note 54.
Figure 7. LTC1147 Layout Diagram (See Board Layout Checklist)
1
2
3
4
8
7
6
5
V
IN
C
T
I
TH
SENSE
–
PDRIVE
SENSE
+
LTC1147-3.3
LTC1147-5
(LTC1147L)
SHUTDOWN
+
1µF
3300pF
1k
390pF
1000pF
+
C
IN
P-CH LR
SENSE
+
C
OUT
+
–
V
OUT
+
–
V
IN
BOLD LINES INDICATE HIGH CURRENT PATHS
LTC1147 • F07
D1
100pF
R1
R2
OUTPUT DIVIDER
REQUIRED WITH
ADJUSTABLE
VERSION ONLY
SHDN
(V
FB
)
GND
