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MMBF4393LT3G

P1-P3P4-P6
MMBF4391LT1G, SMMBF4391LT1G, MMBF4392LT1G, MMBF4393LT1G
http://onsemi.com
4
Figure 5. Switching Time Test Circuit
Figure 6. Typical Forward Transfer Admittance
Figure 7. Typical Capacitance
I
D
, DRAIN CURRENT (mA)
2.0
5.0
3.0
7.0
0.5 1.0 3.0 7.05.0 5030
10
20
0.7 2.0 10 20
, FORWARD TRANSFER ADMITTANCE (mmhos)
fs
V
10
2.0
15
3.0
5.0
7.0
0.5 1.0 3.0 305.00.30.1 100.050.03
V
R
, REVERSE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
T
channel
= 25°C
V
DS
= 15 V
T
channel
= 25°C
(C
ds
is negligible
C
gs
V
DD
V
GG
R
GG
R
T
R
GEN
50 W
V
GEN
R
K
R
D
OUTPUT
INPUT
50
W
50
W
SET V
DS(off)
= 10 V
INPUT PULSE
t
r
≤ 0.25 ns
t
f
≤ 0.5 ns
PULSE WIDTH = 2.0 ms
DUTY CYCLE ≤ 2.0%
R
GG
> R
K
R
D'
= R
D
(R
T
+ 50)
R
D
+ R
T
+ 50
Figure 8. Effect of Gate−Source Voltage
on Drain−Source Resistance
80
120
160
200
50
1.0 3.0
170
5.0
20-10-40
2.0
80 140-70
V
GS
, GATE-SOURCE VOLTAGE (VOLTS)
r
4.00
40
100 mA
125 mA
75 mA50 mA
25 mA
I
DSS
= 10
mA
T
channel
= 25°C
Figure 9. Effect of Temperature on Drain−Source
On−State Resistance
1.8
1.0
2.0
1.2
1.4
1.6
0.8
0.6
0.4
I
D
= 1.0 mA
V
GS
= 0
, DRAIN-SOURCE ON-STATE
DS(on)
RESISTANCE (NORMALIZED)
T
channel
, CHANNEL TEMPERATURE (°C)
1.5
1.0
C
gd
110
6.0 7.0 8.0
0
r , DRAIN-SOURCE ON-STATE
DS(on)
RESISTANCE (OHMS)
MMBF4393
MMBF4392
MMBF4391
NOTE 1
The switching characteristics shown above were measured using
a test circuit similar to Figure 5. At the beginning of the switching
interval, the gate voltage is at Gate Supply Voltage (−V
GG
). The
Drain−Source Voltage (V
DS
) is slightly lower than Drain Supply
Voltage (V
DD
) due to the voltage divider. Thus Reverse Transfer
Capacitance (C
rss
) of Gate−Drain Capacitance (C
gd
) is charged to
V
GG
+ V
DS
.
During the turn−on interval, Gate−Source Capacitance (C
gs
)
discharges through the series combination of R
Gen
and R
K
. C
gd
must
discharge to V
DS(on)
through R
G
and R
K
in series with the parallel
combination of effective load impedance (R’
D
) and Drain−Source
Resistance (r
DS
). During the turn−off, this charge flow is reversed.
Predicting turn−on time is somewhat difficult as the channel
resistance r
DS
is a function of the gate−source voltage. While C
gs
discharges, V
GS
approaches zero and r
DS
decreases. Since C
gd
discharges through r
DS
, turn−on time is non−linear. During turn−off,
the situation is reversed with r
DS
increasing as C
gd
charges.
The above switching curves show two impedance conditions; 1)
R
K
is equal to R
D’
which simulates the switching behavior of
cascaded stages where the driving source impedance is normally the
load impedance of the previous stage, and 2) R
K
= 0 (low
impedance) the driving source impedance is that of the generator.
MMBF4391LT1G, SMMBF4391LT1G, MMBF4392LT1G, MMBF4393LT1G
http://onsemi.com
5
Figure 10. Effect of I
DSS
on Drain−Source
Resistance and Gate−Source Voltage
I
DSS
, ZERO-GATE VOLTAGE DRAIN CURRENT (mA)
, DRAIN-SOURCE ON-STATE
DS(on)
r
20
10
30
40
50
30 40 50 60
70
20
RESISTANCE (OHMS)
0
10
0
1.0
2.0
3.0
4.0
5.0
, GATE-SOURCE VOLTAGE
GS
V
(VOLTS)
T
channel
= 25°C
V
GS(off)
r
DS(on)
@ V
GS
= 0
6.0
7.0
8.0
9.0
10
70
60
80
90
100
80 90 100 110 120 130 140 150
NOTE 2
The Zero−Gate−Voltage Drain Current (I
DSS
) is the
principle determinant of other J−FET characteristics.
Figure 10 shows the relationship of Gate−Source Off
Voltage (V
GS(off)
) and Drain−Source On Resistance
(r
DS(on)
) to I
DSS
. Most of the devices will be within
±10% of the values shown in Figure 10. This data will
be useful in predicting the characteristic variations for
a given part number.
For example:
Unknown
r
DS(on)
and V
GS
range for an MMBF4392
The electrical characteristics table indicates that an
MMBF4392 has an I
DSS
range of 25 to 75 mA. Figure
10 shows r
DS(on)
= 52 W for I
DSS
= 25 mA and 30 W for
I
DSS
= 75 mA. The corresponding V
GS
values are 2.2 V
and 4.8 V.
MMBF4391LT1G, SMMBF4391LT1G, MMBF4392LT1G, MMBF4393LT1G
http://onsemi.com
6
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318−08
ISSUE AP
D
A1
3
12
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM
THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
ǒ
mm
inches
Ǔ
SCALE 10:1
0.8
0.031
0.9
0.035
0.95
0.037
0.95
0.037
2.0
0.079
SOLDERING FOOTPRINT
VIEW C
L
0.25
L1
q
e
E
E
b
A
SEE VIEW C
DIM
A
MIN NOM MAX MIN
MILLIMETERS
0.89 1.00 1.11 0.035
INCHES
A1 0.01 0.06 0.10 0.001
b 0.37 0.44 0.50 0.015
c 0.09 0.13 0.18 0.003
D 2.80 2.90 3.04 0.110
E 1.20 1.30 1.40 0.047
e 1.78 1.90 2.04 0.070
L 0.10 0.20 0.30 0.004
0.040 0.044
0.002 0.004
0.018 0.020
0.005 0.007
0.114 0.120
0.051 0.055
0.075 0.081
0.008 0.012
NOM MAX
L1
H
2.10 2.40 2.64 0.083 0.094 0.104
H
E
0.35 0.54 0.69 0.014 0.021 0.029
c
0 −−− 10 0 −−− 10
q
°°°°
STYLE 10:
PIN 1. DRAIN
2. SOURCE
3. GATE
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MMBF4391LT1/D
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P1-P3P4-P6

MMBF4393LT3G

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JFET SS JFET NCH 30V TR
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