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ADF4106SCPZ-EP-R7

P1-P3P4-P6P7-P9P10-P10
PLL Frequency Synthesizer
Enhanced Product
ADF4106-EP
FEATURES
6.0 GHz bandwidth
2.7 V to 3.3 V power supply
Separate charge pump supply (V
P
) allows extended tuning
voltage in 3 V systems
Programmable dual-modulus prescaler
8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
Support defense and aerospace applications (AQEC)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available upon request
APPLICATIONS
Broadband wireless access
Satellite systems
Instrumentation
Wireless LANS
Base stations for wireless radios
GENERAL DESCRIPTION
The ADF4106-EP frequency synthesizer can be used to
implement local oscillators in the up-conversion and down-
conversion sections of wireless receivers and transmitters. It
consists of a low noise, digital phase frequency detector (PFD),
a precision charge pump, a programmable reference divider,
programmable A counter and B counter, and a dual-modulus
prescaler (P/P + 1). The A (6-bit) counter and B (13-bit) counter, in
conjunction with the dual-modulus prescaler (P/P + 1), implement
an N divider (N = BP + A). In addition, the 14-bit reference
counter (R counter) allows selectable REF
IN
frequencies at the
PFD input. A complete phase-locked loop (PLL) can be
implemented if the synthesizer is used with an external loop
filter and voltage controlled oscillator (VCO). Its very high
bandwidth means that frequency doublers can be eliminated in
many high frequency systems, simplifying system architecture
and reducing cost.
Additional application and technical information can be found
in the ADF4106 data sheet.
FUNCTIONAL BLOCK DIAGRAM
CLK
DATA
LE
REF
IN
RF
IN
A
RF
IN
B
24-BIT INPUT
REGISTER
SD
OUT
AV
DD
DV
DD
CE
AGND
DGND
14-BIT
R COUNTER
R COUNTER
LATCH
22
14
FUNCTION
LATCH
A, B COUNTER
LATCH
FROM
FUNCTION
LATCH
PRESCALER
P/P + 1
N = BP + A
LOAD
LOAD
13-BIT
B COUNTER
6-BIT
A COUNTER
6
19
13
M3 M2 M1
MUX
SD
OUT
AV
DD
HIGH Z
MUXOUT
CPGND
R
SET
V
P
CP
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
REFERENCE
CHARGE
PUMP
CURRENT
SETTING 1
ADF4106-EP
CPI3 CPI2 CPI1
CPI6 CPI5 CPI4
CURRENT
SETTING 2
09272-001
F
igure 1.
Re
v. C
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
O
ne Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2014 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
ADF4106-EP Enhanced Product
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characterisitics ............................................................... 4
Absolute Maximum Ratings ............................................................5
ESD Caution...................................................................................5
Pin Configurations and Function Descriptions ............................6
Typical Performance Characteristics ..............................................7
PCB Design Guidelines for Chip Scale Package............................9
Outline Dimensions ....................................................................... 10
Ordering Guide .......................................................................... 10
REVISION HISTORY
11/14—Rev. B to Rev. C
Change to Table 1 ............................................................................. 3
Change to Table 2 ............................................................................. 4
Changes to Table 3 ............................................................................ 5
8/
12—Rev. A to Rev. B
Changes to Table 3 ............................................................................ 5
Updated Outline Dimensions ....................................................... 10
Changes to Ordering Guide .......................................................... 10
11
/10—Rev. 0 to Rev. A
Changes to Figure 6 .......................................................................... 7
Changes to Figure 11 ........................................................................ 8
Changes to Ordering Guide .......................................................... 10
8/10—Re
vision 0: Initial Version
Rev. C | Page 2 of 10
Enhanced Product ADF4106-EP
SPECIFICATIONS
AV
DD
= DV
DD
= 3 V ± 10%, AV
DD
≤ V
P
≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
SET
= 5.1 kΩ, dBm referred to 50 Ω, T
A
= T
MAX
to T
MIN
,
unless otherwise noted.
Table 1.
Parameter S Version
1
Unit Test Conditions/Comments
RF CHARACTERISTICS
RF Input Frequency (RF
IN
) 0.5/6.0 GHz min/max For lower frequencies, ensure slew rate (SR) > 320 V/µs
RF Input Sensitivity −10/0 dBm min/max
Maximum Allowable Prescaler Output Frequency
2
300 MHz max P = 8
325 MHz P = 16
REF
IN
CHARACTERISTICS
REF
IN
Input Frequency 20/300 MHz min/max For f < 20 MHz, ensure SR > 50 V/µs
REF
IN
Input Sensitivity
3
0.8/V
DD
V p-p min/max Biased at AV
DD
/2
4
REF
IN
Input Capacitance 10 pF max
REF
IN
Input Current ±100 µA max
PHASE DETECTOR
Phase Detector Frequency
5
104
MHz max
ABP = 0, 0 (2.9 ns antibacklash pulse width)
CHARGE PUMP
I
CP
Sink/Source
High Value 5 mA typ With R
SET
= 5.1 kΩ
Low Value 625 µA typ
Absolute Accuracy 2.5 % typ With R
SET
= 5.1 kΩ
R
SET
Range 3.0/11 kΩ typ
I
CP
Three-State Leakage 2 nA max 1 nA typical; T
A
= 25°C
Sink and Source Current Matching 2 % typ 0.5 V ≤ V
CP
≤ V
P
− 0.5 V
I
CP
vs. V
CP
1.5 % typ 0.5 V ≤ V
CP
≤ V
P
− 0.5 V
I
CP
vs. Temperature 2 % typ V
CP
= V
P
/2
LOGIC INPUTS
V
IH
, Input High Voltage 1.4 V min
V
IL
, Input Low Voltage 0.6 V max
I
INH
, I
INL
, Input Current ±1 µA max
C
IN
, Input Capacitance 10 pF max
LOGIC OUTPUTS
V
OH
, Output High Voltage 1.4 V min Open-drain output chosen, 1 kΩ pull-up resistor to 1.8 V
V
DD
− 0.4 V min CMOS output chosen
I
OH
100 µA max
V
OL
, Output Low Voltage 0.4 V max I
OL
= 500 µA
POWER SUPPLIES
AV
DD
2.7/3.3 V min/V max
DV
DD
AV
DD
V
P
AV
DD
/5.5 V min/V max AV
DD
≤ V
P
≤ 5.5 V
I
DD
6
(AI
DD
+ DI
DD
) 11 mA max 9.0 mA typical
I
DD
7
(AI
DD
+ DI
DD
) 11.5 mA max 9.5 mA typical
I
DD
8
(AI
DD
+ DI
DD
)
13
mA max
10.5 mA typical
I
P
0.4
mA max
T
A
= 25°C
Power-Down Mode
9
(AI
DD
+ DI
DD
) 10 µA typ
Rev. C | Page 3 of 10
P1-P3P4-P6P7-P9P10-P10

ADF4106SCPZ-EP-R7

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Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL Freq Synthesizer
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