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ADF4106SCPZ-EP-R7

P1-P3P4-P6P7-P9P10-P10
ADF4106-EP Enhanced Product
Parameter S Version
1
Unit Test Conditions/Comments
NOISE CHARACTERISTICS
Normalized Phase Noise Floor (PN
SYNTH
)
10
−223 dBc/Hz typ PLL loop BW = 500 kHz
Normalized 1/f Noise (PN
1_f
)
11
−122 dBc/Hz typ Measured at 10 kHz offset; normalized to 1 GHz
Phase Noise Performance
12
VCO output
900 MHz
13
−92.5
dBc/Hz typ
1 kHz offset and 200 kHz PFD frequency
5800 MHz
14
−76.5 dBc/Hz typ 1 kHz offset and 200 kHz PFD frequency
5800 MHz
15
−83.5 dBc/Hz typ 1 kHz offset and 1 MHz PFD frequency
Spurious Signals
900 MHz
13
−90/−92 dBc typ 200 kHz/400 kHz and 200 kHz PFD frequency
5800 MHz
14
−65/−70 dBc typ 200 kHz/400 kHz and 200 kHz PFD frequency
5800 MHz
15
−70/−75 dBc typ 1 MHz/2 MHz and 1 MHz PFD frequency
1
Operating temperature range is −55°C to +125°C.
2
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
3
AV
DD
= DV
DD
= 3 V.
4
AC coupling ensures AV
DD
/2 bias.
5
Guaranteed by design. Sample tested to ensure compliance.
6
T
A
= 25°C; AV
DD
= DV
DD
= 3 V; P = 16; RF
IN
= 900 MHz.
7
T
A
= 25°C; AV
DD
= DV
DD
= 3 V; P = 16; RF
IN
= 2.0 GHz.
8
T
A
= 25°C; AV
DD
= DV
DD
= 3 V; P = 32; RF
IN
= 6.0 GHz.
9
T
A
= 25°C; AV
DD
= DV
DD
= 3.3 V; R = 16383; A = 63; B = 891; P = 32; RF
IN
= 6.0 GHz.
10
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log F
PFD
. PN
SYNTH
= PN
TOT
− 10 log F
PFD
− 20 log N.
11
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, f
RF
, and at a
frequency offset, f, is given by PN = P
1_f
+ 10log(10 kHz/f) + 20log(f
RF
/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
12
The phase noise is measured with the EVAL-ADF4106-EB1 evaluation board and the Agilent E4440A spectrum analyzer. The spectrum analyzer provides the REF
IN
for
the synthesizer (f
REFOUT
= 10 MHz @ 0 dBm).
13
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; offset frequency = 1 kHz; f
RF
= 900 MHz; N = 4500; loop B/W = 20 kHz.
14
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; offset frequency = 1 kHz; f
RF
= 5800 MHz; N = 29,000; loop B/W = 20 kHz.
15
f
REFIN
= 10 MHz; f
PFD
= 1 MHz; offset frequency = 1 kHz; f
RF
= 5800 MHz; N = 5800; loop B/W = 100 kHz.
TIMING CHARACTERISITICS
AV
DD
= DV
DD
= 3 V ± 10%, AV
DD
≤ V
P
≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
SET
= 5.1 kΩ, dBm referred to 50 Ω, T
A
= T
MAX
to T
MIN
,
unless otherwise noted.
Table 2.
Parameter Limit
1
(B Version) Unit Test Conditions/Comments
t
1
10 ns min DATA to CLOCK Setup Time
t
2
ns min
DATA to CLOCK Hold Time
t
3
25 ns min CLOCK High Duration
t
4
25 ns min CLOCK Low Duration
t
5
10 ns min CLOCK to LE Setup Time
t
6
20 ns min LE Pulse Width
1
Operating temperature range (S Version) is –55°C to +125°C.
Timing Diagram
CLOCK
DB22
DB2
DATA
LE
t
1
LE
DB23 (MSB)
t
2
DB1 (CONTROL
BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
3
t
4
t
6
t
5
09272-002
Fig
ure 2. Timing Diagram
Rev. C | Page 4 of 10
Enhanced Product ADF4106-EP
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AV
DD
to GND
1
−0.3 V to + 3.6 V
AV
DD
to DV
DD
−0.3 V to + 0.3 V
V
P
to GND −0.3 V to + 5.8 V
V
P
to AV
DD
−0.3 V to + 5.8 V
Digital I/O Voltage to GND −0.3 V to V
DD
+ 0.3 V
Analog I/O Voltage to GND −0.3 V to V
P
+ 0.3 V
REF
IN
, RF
IN
A, RF
IN
B to GND
−0.3 V to V
DD
+ 0.3 V
RF
IN
A to RF
IN
B ±320 mV
Operating Temperature Range
Industrial (S Version) −55°C to +125°C
Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C
θ
JA
Thermal Impedance
16-Lead TSSOP 112°C/W
20-Lead LFCSP (Paddle Soldered) 30.4°C/W
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 40 sec
Transistor Count
CMOS 6425
Bipolar 303
1
GND = AGND = DGND = 0 V.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
Rev. C | Page 5 of 10
ADF4106-EP Enhanced Product
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
R
SET
CP
CPGND
AGND
1
2
3
4
5
6
7
8
RF
IN
B
RF
IN
A
AV
DD
REF
IN
MUXOUT
LE
DATA
CLK
CE
DGND
16
15
14
13
12
11
10
9
V
P
DV
DD
TOP VIEW
(Not to Scale)
ADF4106-EP
NOTES:
1. TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
09272-003
F
igure 3. 16-Lead TSSOP Pin Configuration
15 MUXOUT
14 LE
13 DATA
12 CLK
CPGND 1
AGND 2
AGND 3
20 CP
11 CE
6
7
8
DGND 9
DGND 10
19
18
17
16
RF
IN
B 4
RF
IN
A 5
R
SET
V
P
DV
DD
DV
DD
PIN 1
INDICATOR
TOP VIEW
(Not to Scale)
ADF4106-EP
AV
DD
AV
DD
REF
IN
NOTES
1. TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
2. THE EXPOSED PAD MUST BE
CONNECTED TO AGND.
09272-004
Figure 4. 20-Lead LFCSP Pin Configuration
T
able 4. Pin Function Descriptions
Pin No.
TSSOP
Pin No.
LFCSP Mnemonic Description
1 19 R
SET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the R
SET
pin is 0.66 V. The relationship between I
CP
and R
SET
is
SET
MAXCP
R
I
5.25
=
So, with R
SET
= 5.1 kΩ, I
CP MAX
= 5 mA.
2 20 CP Charge Pump Output. When enabled, this provides ±I
CP
to the external loop filter, which in turn drives
the external VCO.
3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
5 4 RF
IN
B Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a
small bypass capacitor, typically 100 pF.
6 5 RF
IN
A Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
7 6, 7 AV
DD
Analog Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AV
DD
must be the same value as DV
DD
.
8 8 REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and a dc equivalent input
resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
9 9, 10 DGND Digital Ground.
10 11 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into
three-state mode. Taking the pin high powers up the device, depending on the status of the power-
down bit, F2.
11 12 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 13 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input
is a high impedance CMOS input.
13 14 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the four latches with the latch being selected using the control bits.
14 15 MUXOUT
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to
be accessed externally.
15 16, 17 DV
DD
Digital Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DV
DD
must be the same value as AV
DD
.
16 18 V
P
Charge Pump Power Supply. This should be greater than or equal to V
DD
. In systems where V
DD
is 3 V, it
can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.
EP Exposed Pad. The exposed pad must be connected to AGND.
Rev. C | Page 6 of 10
P1-P3P4-P6P7-P9P10-P10

ADF4106SCPZ-EP-R7

Mfr. #:
Buy ADF4106SCPZ-EP-R7
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL Freq Synthesizer
Lifecycle:
New from this manufacturer.
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