PIC18F2XXX/4XXX FAMILY
DS30009622M-page 16 2010-2015 Microchip Technology Inc.
2.5 Entering and Exiting High-Voltage ICSP Program/Verify Mode
As shown in Figure 2-14, the High-Voltage ICSP Program/Verify mode is entered by holding PGC and PGD low and
then raising MCLR
/VPP/RE3 to VIHH (high voltage). Once in this mode, the code memory, data EEPROM (selected
devices only, see Section 3.3 “Data EEPROM Programming”), ID locations and Configuration bits can be accessed
and programmed in serial fashion. Figure 2-15 shows the exit sequence.
The sequence that enters the device into the Program/Verify mode places all unused I/Os in the high-impedance state.
FIGURE 2-14: ENTERING HIGH-VOLTAGE PROGRAM/VERIFY MODE
FIGURE 2-15: EXITING HIGH-VOLTAGE PROGRAM/VERIFY MODE
P12
PGD
PGD = Input
PGC
VDD
D110
P13
P1
MCLR/VPP/RE3
MCLR/VPP/RE3
P16
PGD
PGD = Input
PGC
VDD
D110
P17
P1
2010-2015 Microchip Technology Inc. DS30009622M-page 17
PIC18F2XXX/4XXX FAMILY
2.6 Entering and Exiting Low-Voltage ICSP Program/Verify Mode
When the LVP Configuration bit is1’ (see Section 5.3 “Single-Supply ICSP Programming”), the Low-Voltage ICSP
mode is enabled. As shown in Figure 2-16, Low-Voltage ICSP Program/Verify mode is entered by holding PGC and
PGD low, placing a logic high on PGM and then raising MCLR
/VPP/RE3 to VIH. In this mode, the RB5/PGM pin is
dedicated to the programming function and ceases to be a general purpose I/O pin. Figure 2-17 shows the exit
sequence.
The sequence that enters the device into the Program/Verify mode places all unused I/Os in the high-impedance state.
FIGURE 2-16: ENTERING LOW-VOLTAGE PROGRAM/VERIFY MODE
FIGURE 2-17: EXITING LOW-VOLTAGE PROGRAM/VERIFY MODE
MCLR/VPP/RE3
P12
PGD
PGD = Input
PGC
PGM
P15
VDD
VIH
VIH
MCLR/VPP/RE3
P16
PGD
PGD = Input
PGC
PGM
P18
VDD
VIH
VIH
PIC18F2XXX/4XXX FAMILY
DS30009622M-page 18 2010-2015 Microchip Technology Inc.
2.7 Serial Program/Verify Operation
The PGC pin is used as a clock input pin and the PGD pin is used for entering command bits and data input/output
during serial operation. Commands and data are transmitted on the rising edge of PGC, latched on the falling edge of
PGC and are Least Significant bit (LSb) first.
2.7.1 4-BIT COMMANDS
All instructions are 20 bits, consisting of a leading 4-bit command followed by a 16-bit operand, which depends on the type
of command being executed. To input a command, PGC is cycled four times. The commands needed for programming
and verification are shown in Table 2-8.
Depending on the 4-bit command, the 16-bit operand represents 16 bits of input data or 8 bits of input data and 8 bits
of output data.
Throughout this specification, commands and data are presented as illustrated in Table 2-9. The 4-bit command is shown
Most Significant bit (MSb) first. The command operand, or “Data Payload”, is shown as <MSB><LSB>. Figure 2-18
demonstrates how to serially present a 20-bit command/operand to the device.
2.7.2 CORE INSTRUCTION
The core instruction passes a 16-bit instruction to the CPU core for execution. This is needed to set up registers as
appropriate for use with other commands.
TABLE 2-8: COMMANDS FOR PROGRAMMING
TABLE 2-9: SAMPLE COMMAND SEQUENCE
Description 4-Bit Command
Core Instruction
(Shift in16-bit instruction)
0000
Shift Out TABLAT Register 0010
Table Read 1000
Table Read, Post-Increment 1001
Table Read, Post-Decrement 1010
Table Read, Pre-Increment 1011
Table Write 1100
Table Write, Post-Increment by 2 1101
Table Write, Start Programming,
Post-Increment by 2
1110
Table Write, Start Programming 1111
4-Bit Command Data Payload Core Instruction
1101 3C 40 Table Write,
post-increment by 2

PIC18F4410-I/PT

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Microchip Technology
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8-bit Microcontrollers - MCU 16KB 768 RAM 36I/O
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