2010-2015 Microchip Technology Inc. DS30009622M-page 45
PIC18F2XXX/4XXX FAMILY
WRT5 CONFIG6L Write Protection bit (Block 5 code memory area)
(PIC18F2685 and PIC18F4685 devices only)
1 = Block 5 is not write-protected
0 = Block 5 is write-protected
WRT4 CONFIG6L Write Protection bit (Block 4 code memory area)
(PIC18F2682/2685 and PIC18F4682/4685 devices only)
1 = Block 4 is not write-protected
0 = Block 4 is write-protected
WRT3 CONFIG6L Write Protection bit (Block 3 code memory area)
1 = Block 3 is not write-protected
0 = Block 3 is write-protected
WRT2 CONFIG6L Write Protection bit (Block 2 code memory area)
1 = Block 2 is not write-protected
0 = Block 2 is write-protected
WRT1 CONFIG6L Write Protection bit (Block 1 code memory area)
1 = Block 1 is not write-protected
0 = Block 1 is write-protected
WRT0 CONFIG6L Write Protection bit (Block 0 code memory area)
1 = Block 0 is not write-protected
0 = Block 0 is write-protected
WRTD CONFIG6H Write Protection bit (Data EEPROM)
1 = Data EEPROM is not write-protected
0 = Data EEPROM is write-protected
WRTB CONFIG6H Write Protection bit (Boot Block memory area)
1 = Boot Block is not write-protected
0 = Boot Block is write-protected
WRTC CONFIG6H Write Protection bit (Configuration registers)
1 = Configuration registers are not write-protected
0 = Configuration registers are write-protected
EBTR5 CONFIG7L Table Read Protection bit (Block 5 code memory area)
(PIC18F2685 and PIC18F4685 devices only)
1 = Block 5 is not protected from Table Reads executed in other blocks
0 = Block 5 is protected from Table Reads executed in other blocks
EBTR4 CONFIG7L Table Read Protection bit (Block 4 code memory area)
(PIC18F2682/2685 and PIC18F4682/4685 devices only)
1 = Block 4 is not protected from Table Reads executed in other blocks
0 = Block 4 is protected from Table Reads executed in other blocks
EBTR3 CONFIG7L Table Read Protection bit (Block 3 code memory area)
1 = Block 3 is not protected from Table Reads executed in other blocks
0 = Block 3 is protected from Table Reads executed in other blocks
EBTR2 CONFIG7L Table Read Protection bit (Block 2 code memory area)
1 = Block 2 is not protected from Table Reads executed in other blocks
0 = Block 2 is protected from Table Reads executed in other blocks
EBTR1 CONFIG7L Table Read Protection bit (Block 1 code memory area)
1 = Block 1 is not protected from Table Reads executed in other blocks
0 = Block 1 is protected from Table Reads executed in other blocks
TABLE 5-3: PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED)
Bit Name
Configuration
Words
Description
Note 1: The BBSIZ bits, BBSIZ<1:0> and BBSIZ<2:1> bits, cannot be changed once any of the following
code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0.
2: Not available in PIC18FXX8X and PIC18F2450/4450 devices.
