PIC18LF4510-I/PT Datasheet PIC18F4321-I/PT, PIC18F4410-I/PT, PIC18F4510-I/PT | P31-P33

 2010-2015 Microchip Technology Inc. DS30009622M-page 31

PIC18F2XXX/4XXX FAMILY

3.4 ID Location Programming

The ID locations are programmed much like the code memory. The ID registers are mapped in addresses, 200000h

through 200007h. These locations read out normally even after code protection.

Table 3-8 demonstrates the code sequence required to write the ID locations.

In order to modify the ID locations, refer to the methodology described in Section 3.2.1 “Modifying Code Memory”.

As with code memory, the ID locations must be erased before being modified.

TABLE 3-8: WRITE ID SEQUENCE

3.5 Boot Block Programming

The code sequence detailed in Table 3-5 should be used, except that the address used in “Step 2” will be in the range

of 000000h to 0007FFh.

3.6 Configuration Bits Programming

Unlike code memory, the Configuration bits are programmed a byte at a time. The Table Write, Begin Programming 4-bit

command (‘1111’) is used, but only eight bits of the following 16-bit payload will be written. The LSB of the payload will be

written to even addresses and the MSB will be written to odd addresses. The code sequence to program two consecutive

configuration locations is shown in Table 3-9.

Note: The user only needs to fill the first 8 bytes of the write buffer in order to write the ID locations.

4-Bit

Command

Data Payload Core Instruction

Step 1: Direct access to code memory and enable writes.

0000

8E A6

9C A6

BSF EECON1, EEPGD

BCF EECON1, CFGS

Step 2: Load write buffer with 8 bytes and write.

0000

1101

1111

0000

0E 20

6E F8

0E 00

6E F7

0E 00

6E F6

00 00

MOVLW 20h

MOVWF TBLPTRU

MOVLW 00h

MOVWF TBLPTRH

MOVLW 00h

MOVWF TBLPTRL

Write 2 bytes and post-increment address by 2.

Write 2 bytes and start programming.

NOP - hold PGC high for time P9 and low for time P10.

Note: The address must be explicitly written for each byte programmed. The addresses can not be incremented

in this mode.

PIC18F2XXX/4XXX FAMILY

DS30009622M-page 32  2010-2015 Microchip Technology Inc.

TABLE 3-9: SET ADDRESS POINTER TO CONFIGURATION LOCATION

FIGURE 3-8: CONFIGURATION PROGRAMMING FLOW

4-Bit

Command

Data Payload Core Instruction

Step 1: Enable writes and direct access to configuration memory.

0000

8E A6

8C A6

BSF EECON1, EEPGD

BSF EECON1, CFGS

Step 2: Set Table Pointer for configuration byte to be written. Write even/odd addresses.

(1)

0000

1111

0000

1111

0000

0E 30

6E F8

0E 00

6E F7

0E 00

6E F6

00 00

0E 01

6E F6

00 00

MOVLW 30h

MOVWF TBLPTRU

MOVLW 00h

MOVWF TBLPRTH

MOVLW 00h

MOVWF TBLPTRL

Load 2 bytes and start programming.

NOP - hold PGC high for time P9 and low for time P10.

MOVLW 01h

MOVWF TBLPTRL

Load 2 bytes and start programming.

NOP - hold PGC high for time P9 and low for time P10.

Note 1: Enabling the write protection of Configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of the

Configuration bits. Always write all the Configuration bits before enabling the write protection for Configuration bits.

Load Even

Configuration

Start

Program Program

MSB

Delay P9 and P10

Time for Write

LSB

Load Odd

Configuration

Address

Done

Start

Delay P9 and P10

Time for Write

Done

 2010-2015 Microchip Technology Inc. DS30009622M-page 33

PIC18F2XXX/4XXX FAMILY

4.0 READING THE DEVICE

4.1 Read Code Memory, ID Locations and Configuration Bits

Code memory is accessed, one byte at a time, via the 4-bit command, ‘1001’ (Table Read, post-increment). The

contents of memory pointed to by the Table Pointer (TBLPTRU:TBLPTRH:TBLPTRL) are serially output on PGD.

The 4-bit command is shifted in, LSb first. The read is executed during the next eight clocks, then shifted out on PGD

during the last eight clocks, LSb to MSb. A delay of P6 must be introduced after the falling edge of the 8th PGC of the

operand to allow PGD to transition from an input to an output. During this time, PGC must be held low (see Figure 4-1).

This operation also increments the Table Pointer by one, pointing to the next byte in code memory for the next read.

This technique will work to read any memory in the 000000h to 3FFFFFh address space, so it also applies to the reading

of the ID and Configuration registers.

TABLE 4-1: READ CODE MEMORY SEQUENCE

FIGURE 4-1: TABLE READ POST-INCREMENT INSTRUCTION TIMING (1001)

4-Bit

Command

Data Payload Core Instruction

Step 1: Set Table Pointer.

0000

0E <Addr[21:16]>

6E F8

0E <Addr[15:8]>

6E F7

0E <Addr[7:0]>

6E F6

MOVLW Addr[21:16]

MOVWF TBLPTRU

MOVLW <Addr[15:8]>

MOVWF TBLPTRH

MOVLW <Addr[7:0]>

MOVWF TBLPTRL

Step 2: Read memory and then shift out on PGD, LSb to MSb.

1001 00 00 TBLRD *+

1234

PGC

PGD

PGD = Input

Shift Data Out

PGD = Output

5678

1234

P5A

10 11 13 15 161412

Fetch Next 4-Bit Command

1001

PGD = Input

LSb MSb

1234

nnnn

P14

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P56

PIC18LF4510-I/PT

Mfr. #:

Buy PIC18LF4510-I/PT

Manufacturer:

Microchip Technology

Description:

8-bit Microcontrollers - MCU 32KB 1536 RAM 36I/O

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

PIC18LF4510-I/PT

PIC18LF4510-I/PT

Products related to this Datasheet