AD22057
–4–
REV. A
Figure 3 shows a general method for trimming the gain, either
upward or downward, by an amount dependent on the resistor,
R. The gain range, expressed as a percentage of the overall gain,
is given by (10 MΩ/R)%. Thus, the adjustment range would be
±2% for R = 5 MΩ; ± 10% for R = 1 MΩ, etc.
AD22057
+IN OFS +V
S
OUT
–IN GND A1 A2
V
DM
V
CM
R
(SEE TEXT)
V
= DIFFERENTIAL VOLTAGE, V
= COMMOM-MODE VOLTAGE
ANALOG
OUTPUT
6GAIN ADJUST
20kV MIN
ANALOG
COMMON
Figure 3. Altering Gain to Accommodate Transducer
Scaling Error
In addition to the method above, another method may be used
to vary the gain. Many applications will call for a gain higher
than ×20, and some require a lower gain. Both of these situa-
tions are readily accommodated by the addition of one external
resistor, plus an optional potentiometer if gain adjustment is
required (for example, to absorb a calibration error in a trans-
ducer).
Decreasing the Gain. See Figure 4. Since the output of the
preamplifier has an output resistance of 100 kΩ, an external
resistor connected from Pin 4 to ground will precisely lower the
gain by a factor R/(100k+R). When configuring the AD22057
for any gain, the maximum input and the power supply being
used should be considered, since either the preamplifier or the
output buffer will reach its full-scale output (approximately
V
S
– 0.2 V) with large differential input voltages. The input of
the AD22057 is limited to no greater than (V – 0.2)/10, for
overall gains less than 10, since the preamplifier, with its fixed
gain of ×10, reaches its full scale output before the output
buffer. For V
S
= 5 V this is 0.48 V. For gains greater than 10,
however, the swing at the buffer output reaches its full-scale first
and limits the AD22057 input to (V
S
– 0.2)/G, where G is the
overall gain. Increasing the power supply voltage increases the
allowable maximum input. For V
S
= 5 V and a nominal gain of
20, the maximum input is 240 mV.
The overall bandwidth is unaffected by changes in gain using
this method, although there may be a small offset voltage due to
the imbalance in source resistances at the input to A2. In many
cases this can be ignored but, if desired, can be nulled by insert-
ing a resistor in series with Pin 4 (at “Point X” in Figure 4) of
value 100 kΩ minus the parallel sum of R and 100 kΩ. For
example, with R = 100 kΩ (giving a total gain of ×10), the op-
tional offset nulling resistor is 50 kΩ.
AD22057
+IN OFS
+V
S
OUT
–IN
GND A1 A2
V
DM
V
CM
R
ANALOG
OUTPUT
ANALOG
COMMON
POINT X
(SEE TEXT)
GAIN = –––––––––
20R
R + 100kV
R = 100k –––––––––
GAIN
20 – GAIN
Figure 4. Achieving Gains Less Than
×
20
Increasing the Gain. The gain can be raised by connecting a
resistor from the output of the buffer amplifier (Pin 5) to its
noninverting input (Pin 4) as shown in Figure 5. The gain is
now multiplied by the factor R/(R–100k); for example, it is
doubled for R = 200 kΩ. Overall gains of up to ×160 (R = 114 kΩ)
are readily achievable in this way. Note, however, that the accu-
racy of the gain becomes critically dependent on resistor value at
high gains. Also, the effective input offset voltage at Pins 1 and
8 (about six times the actual offset of A1) limits the part’s use in
very high gain, dc-coupled applications. The gain may be trimmed
by using a fixed and variable resistor in series (see, for example,
Figure 10).
AD22057
+IN OFS +V
S
OUT
–IN
GND A1 A2
V
DM
V
CM
ANALOG
OUTPUT
ANALOG
COMMON
POINT X
(SEE TEXT)
GAIN = –––––––––
20R
R – 100kV
R = 100k –––––––––
GAIN
GAIN – 20
R
Figure 5. Achieving Gains Greater Than
×
20
Once again, a small offset voltage will arise from an imbalance
in source resistances and the finite bias currents inherently
present at the input of A2. In most applications this additional
offset error (about 130 µV at ×40) will be comparable with the
specified offset range and will therefore introduce negligible
skew. It may, however, be essentially eliminated by the addition
of a resistor in series with the parallel sum of R and 100 kΩ
(i.e., at “Point X” in Figure 5) so the total series resistance is
maintained at 100 kΩ. For example, at a gain of ×30, when
R = 300 kΩ and the parallel sum of R and 100 kΩ is 75 kΩ, the
padding resistor should be 25 kΩ. A 50 kΩ pot would provide
an offset range of about ±2.25 mV referred to the output, or
±75 µV referred to the attenuator input. A specific example is
shown in Figure 12.
LOW-PASS FILTERING
In many transducer applications it is necessary to filter the sig-
nal to remove spurious high frequency components, including
noise, or to extract the mean value of a fluctuating signal with a
peak-to-average ratio (PAR) greater than unity. For example, a
full wave rectified sinusoid has a PAR of 1.57, a raised cosine
has a PAR of 2 and a half wave sinusoid has a PAR of 3.14.
Signals having large spikes may have PARs of 10 or more.
When implementing a filter, the PAR should be considered so
the output of the AD22057 preamplifier (A1) does not clip
before A2 does, since this nonlinearity would be averaged and
appear as an error at the output. To avoid this error both ampli-
fiers should be made to clip at the same time. This condition is
achieved when the PAR is no greater than the gain of the second
amplifier (2 for the default configuration). For example, if a
PAR of 5 is expected, the gain of A2 should be increased to 5.
Low-pass filters can be implemented in several ways using the
features provided by the AD22057. In the simplest case, a
single-pole filter (20 dB/decade) is formed when the output of
A1 is connected to the input of A2 via the internal 100 kΩ resis-
tor by strapping Pins 3 and 4, and a capacitor added from this
node to ground, as shown in Figure 6. The dc gain remains ×20,
and the gain trim shown in Figure 3 may still be used. If a resis-
tor is added across the capacitor to lower the gain, the corner
