Rev E 11/12/14 2 FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
840002-01 DATA SHEET
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1 F_SEL0 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels.
2 nXTAL_SEL Input Pulldown
Selects between crystal or TEST_CLK inputs as the PLL reference
source. When HIGH, selects TEST_CLK. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.
3 TEST_CLK Input Pulldown Single-ended test clock input. LVCMOS/LVTTL interface levels.
4
OE
Input Pullup
Output enable. When logic HIGH, the outputs are active.
When LOW, the outputs are in high-impedance state.
LVCMOS/LVTTL interface levels.
5 MR Input Pulldown
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the active outputs to go low. When Logic LOW,
the internal dividers and the outputs are enabled. LVCMOS/LVTTL
interface levels.
6 nPLL_SEL Input Pulldown
PLL Bypass. When LOW, the output is driven from the VCO output. When
HIGH, the PLL is bypassed and the output frequency = reference clock
frequency/N output divider. LVCMOS/LVTTL interface levels.
7V
DDA
Power Analog supply pin.
8V
DD
Power Core supply pin.
9,
10
XTAL_OUT
XTAL_IN
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the
output.
11 V
DDO
Power Output supply pin.
12, 13
Q1, Q0
Output Single-ended clock outputs. LVCMOS/LVTTL interface levels.
14, 15 GND Power Power supply ground.
16 F_SEL1 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4pF
C
PD
Power Dissipation Capacitance 8 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
R
OUT
Output Impedance
V
DDO
= 3.3V ± 5% 14 17 21
V
DDO
= 2.5V ± 5% 16 21 25
