8©2016 Integrated Device Technology, Inc Revision A April 20, 2016
843N252-45 Data Sheet
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 2A and 2B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 2A. 3.3V LVPECL Output Termination Figure 2B. 3.3V LVPECL Output Termination
Schematic Example
Figure 3 shows an example of 843N252-45 application schematic. In
this example, the device is operated at V
CC
= V
CCA
= V
CCOA
= 3.3V.
If the12pF parallel resonant 25MHz crystal is used; the load
capacitance C1 = 5pF and C2 = 5pF are recommended for frequency
accuracy. If the 18pF parallel resonant 25MHz crystal is used; the
load capacitance C1 = 15pF and C2 = 15pF are recommended.
Depending on the parasitics of the printed circuit board layout, these
values might require a slight adjustment to optimize the frequency
accuracy. Crystals with other load capacitance specifications can be
used. This will require adjusting C1 and C2. For this device, the
crystal load capacitors are required for proper operation.
As with any high speed analog circuitry, the power supply pins are
vulnerable to noise. To achieve optimum jitter performance, power
supply isolation is required. The 843N252-45 provides separate
power supplies to isolate from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
R1
84
R2
84
3.3V
R3
125
R4
125
Z
o
= 50
Z
o
= 50
Input
3.3V
3.3V
+
_
