LTC6412
12
6412fa
PIN FUNCTIONS
GND (Pins 1, 8, 12, 15, 18, 20, 23): Ground. Pins are
connected to each other internally. For best RF performance,
all ground pins should be connected to the printed circuit
board ground plane.
+IN (Pin 2): Positive Signal Input Pin. Has an inter-
nally generated DC Bias. A 10nF DC blocking capacitor is
recommended.
–IN (Pin 3): Negative Signal Input Pin. Has an inter-
nally generated DC Bias. A 10nF DC blocking capacitor is
recommended.
V
CM
(Pins 4, 5): Input Common Mode Voltage Pins. Two
pins are tied together internally and serve as a virtual
ground for the differential inputs, +IN and –IN. Capaci-
tive decoupling to ground with 10nF close to the pins is
recommended to help terminate any residual common
mode input signal.
V
CC
(Pins 6, 13, 19, 24): Positive Power Supply. All
four pins must be tied to the same voltage, usually 3.3V.
Bypass each pin with 1000pF and 0.1μF capacitors close
to the pins.
DECL1 (Pin 7): Decoupling Pin. Serves to reduce internal
noise. Bypass to ground with a 0.1μF capacitor close to
the pin.
+V
G
(Pin 9): Positive Gain Control Pin. Input signal pin used
for positive mode gain control. Otherwise, pin is typically
connected to V
REF
for negative mode gain control. Pin is
internally pulled to ground with a 10k resistor. In positive
gain slope mode, the gain control slope is approximately
+32dB/V at 140MHz with a gain control range of 0.1V to
1.1V.
V
REF
(Pin 10): Internal Bias Voltage Pin. Typically tied to
–V
G
pin for positive gain control or tied to +V
G
for nega-
tive gain control. Determines the midpoint voltage of the
gain-vs-V
G
characteristic. Bypass to ground with 0.1μF
capacitor close to the pin. Not intended for use as an
external reference voltage.
–V
G
(Pin 11): Negative Gain Control Pin. Input signal pin
used for negative mode gain control. Otherwise, pin is
typically connected to V
REF
for positive mode gain con-
trol. Pin is internally pulled to ground with a 10k resistor.
In negative gain slope mode, the gain control slope is
approximately –32dB/V at 140MHz with a gain control
range of 0.1V to 1.1V.
DECL2 (Pin 14): Decoupling Pin. Serves to reduce internal
noise. Bypass to ground with a 1000pF capacitor close
to the pin.
–OUT (Pin 16): Negative Amplifi er Output Pin. A trans-
former with a center tap tied to V
CC
or a choke inductor
is recommended to conduct DC quiescent current to the
open-collector output device. For best performance, DC
bias voltage to –OUT must be within 100mV of V
CC
.
+OUT (Pin 17): Positive Amplifi er Output Pin. A trans-
former with a center tap tied to V
CC
or a choke inductor
is recommended to conduct DC quiescent current to the
open-collector output device. For best performance, DC
bias voltage to +OUT must be within 100mV of V
CC
.
EN (Pin 21): Output Signal Enable Pin. Pin is internally
pulled high with 100kΩ to V
CC
. Assert pin to a low volt-
age to enable the output amplifi er signal. Output amplifi er
impedance and DC current are not affected by the EN state.
Connect pin to ground if enable function is not used.
SHDN (Pin 22): Shutdown Pin. Pin is internally pulled high
with 100kΩ to V
CC
. Assert pin to a low voltage to shut
down the circuit and greatly reduce the supply current.
Proper sequencing of the EN and SHDN pins is required
to avoid non-monotonic output signal behavior. See
Applications Information section for details. Connect pin
to V
CC
if shutdown function is not used.
Exposed Pad (Pin 25): Ground. The Exposed Pad should
have multiple via holes to an underlying ground plane for
low inductance and good thermal dissipation.
