LTC6412IUF#PBF Datasheet LTC6412IUF#PBF, LTC6412CUF#TRPBF, LTC6412IUF#TRPBF | P16-P18

LTC6412

6412fa

APPLICATIONS INFORMATION

grounding and supply decoupling. Failure to provide low

impedance supply and ground at high frequencies can

cause oscillations and increased distortion.

Enable/Shutdown

Both the EN pin and SHDN pin are self-biased to V

through

their respective 100k pull-up resistors, so the default

open-pin state is powered on with the output ampliﬁ er

signal path disabled. Pulling the EN pin low completes

the signal path from the attenuator ladder through the

output ampliﬁ er. The EN pin essentially provides a fast

muting function while the SHDN pin provides slower

power on/off function.

For applications requiring the SHDN function, it is

recommended that the output ampliﬁ er signal path be

disabled with a high EN voltage before transitioning the

SHDN signal. When enabling the ampliﬁ er, allow at least

5ms dwell time between the rising SHDN transition and the

falling EN transition to avoid non-monotonic output signal

behavior though the VGA. The opposite delay sequence

is recommended for the falling SHDN transition, but this

is less critical as the output signal amplitude will drop

abruptly regardless of the EN pin.

SHDN

DWELL

6412 AI01

Layout/Grounding

The high frequency performance of the LTC6412 requires

special attention to proper RF grounding, bias decoupling

and termination. The recommended PCB stack-up for a

4-layer board is shown below for 1oz copper clad FR-4

laminate with a relative dielectric constant, ε

= 4.2-4.5

at 1GHz.

METAL 1

METAL 2

METAL 3

METAL 4

RF SIGNAL

FR4 12-18 MILS

FR4 20-30 MILS

FR4 NOT CRITICAL

GROUND PLANE

POWER PLANE

GND AND LF SIGNAL

6412 AI02

The topside metal and silkscreen drawings for Test Circuit A

illustrate the recommended decoupling capacitor place-

ment, signal routing and grounding. Ground vias directly

beneath the Exposed Pad are critical; use as many as possible.

Ground vias to the other ground pins are less critical.

ESD

The LTC6412 is protected with reverse-biased ESD diodes

on all I/O pins. If any I/O pin is forced one diode drop above

the positive supply or one diode drop below the negative

supply, then large currents may ﬂ ow through the diodes.

No damage to the devices will occur if the current is kept

below 10 mA. The +OUT/–OUT pins have additional series

diodes to the positive supply and can sustain approximately

2V overshoot above the positive supply before conducting

appreciable currents.

Signal Compression Characteristics

The graph entitled, Input and Output P1dB, illustrates

an important characteristic of the LTC6412 VGA. At gain

settings above –5dB, the output ampliﬁ er limits the linear

power handling capability, but at gain settings below

–5dB, the input attenuator ladder limits the linear power

handling capability. The linear input power limitations at

minimum gain do not affect the overall performance of

a signal chain if the preceding mixer or ampliﬁ er stage

exhibits an OP1dB < 19dBm and an OIP3 < 50dBm.

Test Circuits

The fully-differential nature of the LTC6412 design requires

two test circuits to generate the performance information

presented in this data sheet.

Test Circuit A is DC1464A, a 2-port demonstration circuit

with input/output balun transformers to allow for direct

connection to a 2-port network analyzer or other single-

ended 50Ω test system. The balun transformers limit the

high and low frequency performance of the LTC6412 but

allow for simple and reasonably accurate measurements

from 70MHz to 380MHz. The gain control signal is supplied

to either of the V

turrets for DC control measurements

or through the V

GAIN

SMA connector for transient control

signal measurements. Clip leads to the gain control turrets

are susceptible to noise pickup and should be lowpass

LTC6412

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ﬁ ltered to avoid AM upconversion artifacts. While using

the ±V

turrets, a 4.7μF capacitor from the V

GAIN

SMA

input to ground provides an effective lowpass ﬁ lter.

Typical data curves quoted for Test Circuit A are measured

at the plane of the SMA connectors and are NOT corrected

for any losses introduced by the input and output baluns,

estimated at approximately 0.5dB and 1.2dB, respectively.

All typical AC data reported in this data sheet correspond

to Test Circuit A, except for mixed-mode S-parameters of

the form Sdd21, Scc21, etc.

Test Circuit B uses a 4-port network analyzer to measure

differential mode and common mode S-parameters

beyond the frequency limitations imposed by the balun

transformers and associated circuitry. A matching

calibration set establishes the measurement reference

planes shown in Test Circuit B. The output plane is deﬁ ned

at the edge of the package while the input plane is deﬁ ned

at the edge of the input pair of 0402 capacitors. The IC

land and ground via pattern are identical to that shown

for Test Circuit A. The ground via pattern directly beneath

the package is critical to provide the proper RF ground to

produce the RF characteristics quoted in this data sheet.

All mixed-mode S-parameter typical data curves of the

form SxyAB correspond to Test Circuit B following the

deﬁ nitions described in Figures 5 and 6.

Typical Application Circuits

Grounding and supply decoupling should closely follow the

suggested layout shown for Test Circuit A, but the input

and output networks can be customized to suit various

application requirements.

On the input side, the differential port impedance is

very close to 50Ω over all gain settings and application

frequencies. In a differential signal chain, the differential

input signal is easily supplied from a preceding differential

output stage with a suitable DC blocking capacitor of

approximately 10nF. If the system employs a single-ended

input signal to the VGA, then a suitable balun is required

to convert to a differential input signal. The passive

conversion from 50Ω single-ended to 50Ω differential is

most effectively accomplished with a 1:1 transmission-line

balun such as the ETC1-1-13 or MABA-007159. These 1:1

balun devices are relatively inexpensive and offer excellent

APPLICATIONS INFORMATION

electrical characteristics such as low loss, broad band

response and good phase matching.

6412 F01

Figure 1. Top Silkscreen for DC1464A. Test Circuit A

On the output side, the differential port admittance is very

close to 300Ω||1.5pF across all gain settings and application

frequencies. This output port circuit must provide a path for

DC output supply current as well as any balun, matching,

or ﬁ ltering functions required by the application. Thus, the

design options for the output circuitry are more varied. A

brief list of the more common output circuits is shown in

Figure 9 along with a few design guidelines to estimate

component values. Final design simulations should use the

small-signal equivalent circuit model in Figure 8 to properly

account for loading effects of the output terminals.

Figure 9a shows the simplest differential output

conﬁ guration employing two suitable inductors, L1 = L2,

to pass the DC supply current without loading the output

nodes at the application frequency. The PCB trace widths

LTC6412

6412fa

APPLICATIONS INFORMATION

6412 F02

Figure 2. Top Metal for DC1464A. Test Circuit A

Figure 9b shows a further variation of the tuned differential

output where the DC blocking capacitors are brought inside

the tank resonator to participate in the bandpass ﬁ lter and

transform the VGA output impedance to a lower value.

Here too, the C

capacitor can be split into two separate

shunt capacitors to ground, so any common mode noise

is ﬁ ltered as well.

Figure 9c shows a ﬂ ux transformer used to achieve a

50Ω single-ended output. The ﬂ ux transformer does

not provide the large bandwidth typical of the output

transmission-line transformer shown in Figure 3, but it

usually performs well over smaller bandwidths, especially

when tuned with shunt capacitors (not shown). The ﬂ ux

transformer design eliminates DC blocking capacitors and

is attractive in rugged applications where the ampliﬁ er

output is subjected to ESD events and other forms of

transient electrical overstress that do not pass through a

typical RF ﬂ ux transformer such as the MABAES0061.

Figure 9d shows a discrete LC balun suitable for bandwidths

of approximately 15% to 30%. Larger bandwidths are

difﬁ cult to achieve with the number of components shown,

and smaller bandwidths are often limited by component

tolerance effects. Despite these limitations, the discrete

LC balun can be a cost effective output circuit solution.

At resonance, the tuned circuit produces an impedance

transformation along with the differential-to-single-ended

conversion.

DC-Coupled Operation

The LTC6412 is intended for AC-coupled operation. The

translation between the ﬁ xed input DC common mode

voltage and higher open-collector output DC bias point

makes it impractical to use in DC-coupled applications.

from the output pins should be narrow in keeping with

the high impedance of these terminals; 8 to 10mil trace

width on 1oz copper is a good choice. The 0.1μF capacitors

serve to DC block and decouple as needed. These capacitor

values are adequate down to a few MHz and can be scaled

down for higher application frequencies.

If bandpass ﬁ ltering is needed at the VGA output of

Figure 9a, then L1 and L2 can be designed to resonate

with a shunt capacitor, C

, at the frequency of interest,

ω =1/√C

(L1 + L2). Alternately, L1 = L2 can be designed

to resonate with two separate capacitors, C1 = C2, so any

common mode noise is ﬁ ltered as well.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

LTC6412IUF#PBF

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

High Speed Operational Amplifiers 800MHz, 31dB Rng Analog-Controlled VGA

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