SE95_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 2 September 2009 7 of 27
NXP Semiconductors
SE95
Ultra high accuracy digital temperature sensor and thermal watchdog
7.5 Shutdown mode
The device operation mode is selected by programming bit SHUTDOWN of register Conf.
Setting bit SHUTDOWN to logic 1 will put the device into shutdown mode. Resetting bit
SHUTDOWN to logic 0 will return the device to normal mode.
In shutdown mode, the device draws a small current of approximately 7.5 µA and the
power dissipation is minimized; the temperature conversion stops, but the I
2
C-bus
interface remains active and register write/read operation can be performed. If the OS
output is in comparator mode, then it remains unchanged. In interrupt mode, the OS
output is reset.
7.6 Power-up default and power-on reset
The SE95 always powers-up in its default state with:
• Normal operation mode
• OS comparator mode
• T
os
= 80 °C
• T
hyst
= 75 °C
• OS output active state is LOW
• Pointer value is logic 0
When the power supply voltage is dropped below the device power-on reset level of
approximately 1.9 V (POR) and then rises up again, the device will be reset to its default
condition as listed above.
8. I
2
C-bus serial interface
The SE95 can be connected to a compatible 2-wire serial interface I
2
C-bus as a slave
device under the control of a controller or master device, using two device terminals, SCL
and SDA. The controller must provide the SCL clock signal and write/read data to and
from the device through the SDA terminal. Note that if the I
2
C-bus common pull-up
resistors have not been installed as required for I
2
C-bus, then an external pull-up resistor,
approximately 10 kΩ, is needed for each of these two terminals. The bus communication
protocols are described in Section 8.7 “Protocols for writing and reading the registers”.
8.1 Slave address
The SE95 slave address on the I
2
C-bus is partially defined by the logic applied to the
device address pins A2, A1 and A0. Each pin is typically connected either to GND for
logic 0, or to V
CC
for logic 1. These pins represent the three LSB bits of the device 7-bit
address. The other four MSB bits of the address data are preset to 1001 by hard wiring
inside the SE95. Table 4 shows the device's complete address and indicates that up to
8 devices can be connected to the same bus without address conflict. Because the input
pins SCL, SDA and A2 to A0, are not internally biased, it is important that they should not
be left floating in any application.
0Ch is a reserved address for SMBus Alert Response Address (ARA). This is an optional
command from the SMBus specification to allow SMBus devices to respond to an SMBus
master with their slave device if they are generating an interrupt. The SE95 will send a
