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CY2XP24ZXIT

P1-P3P4-P6P7-P9P10-P12
CY2XP24
Crystal to LVPECL Clock Generator
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-15705 Rev. *G Revised April 7, 2011
Features
■ One LVPECL Output Pair
■ Selectable output frequency: 156.25 MHz or 187.5 MHz
■ External crystal frequency: 25 MHz
■ Low root mean square (RMS) phase jitter at 156.25 MHz, using
25 MHz crystal (1.875 MHz to 20 MHz): 0.33 ps (typical)
■ Pb-free 8-Pin thin shrunk small outline package (TSSOP)
Package
■ Supply voltage: 3.3 V or 2.5 V
■ Commercial and industrial temperature ranges
Functional Description
The CY2XP24 is a PLL (phase locked loop) based high
performance clock generator. It is optimized to generate 10 Gb
Ethernet, Fibre Channel, and other high performance clock
frequencies. It produces an output frequency that is either 6.25
times or 7.5 times the crystal frequency. It uses Cypress’s low
noise VCO technology to achieve low phase jitter, that meets
both 10 Gb Ethernet, Fibre Channel, and SATA jitter
requirements. The CY2XP24 has a crystal oscillator interface
input and one LVPECL output pair.
Logic Block Diagram
/4
PHASE
DETECTOR
CRYSTAL
OSCILLATOR
VCO
0 = /25
1 = /30
F_SEL
External
Crystal
XOUT
XIN
CLK
CLK#
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CY2XP24
Document #: 001-15705 Rev. *G Page 2 of 12
Contents
Pinouts ..............................................................................3
Frequency Table ............................................................... 4
Absolute Maximum Conditions ....................................... 4
Operating Conditions .......................................................4
DC Electrical Characteristics ..........................................4
AC Electrical Characteristics ...........................................5
Recommended Crystal Specifications ............................5
Parameter Measurements ................................................ 6
Application Information ................................................... 7
Power Supply Filtering Techniques ............................. 7
Termination for LVPECL Output .................................. 7
Crystal Input Interface ................................................. 7
Ordering Information ........................................................ 8
Ordering Code Definition ............................................. 8
Acronyms ........................................................................ 10
Document Conventions ................................................. 10
Units of Measure ....................................................... 10
Sales, Solutions, and Legal Information ...................... 12
Worldwide Sales and Design Support ....................... 12
Products .................................................................... 12
PSoC Solutions ......................................................... 12
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CY2XP24
Document #: 001-15705 Rev. *G Page 3 of 12
Pinouts
Figure 1. Pin Diagram - 8 Pin TSSOP
1
2
36
7
8
XOUT
XIN F_SEL
VSS
VDD
CLK#
45
VDD
CLK
Table 1. Pin Definitions - 8 Pin TSSOP
Pin Name Type Description
1, 8 VDD Power 3.3 V or 2.5 V power supply. All supply current flows through pin 1
2 VSS Power Ground
3, 4 XOUT, XIN XTAL output and input Parallel resonant crystal interface
5 F_SEL CMOS input Frequency select. When HIGH, the output frequency is 7.5 times of the
crystal frequency. When LOW, the output frequency is 6.25 times of the
crystal frequency
6,7 CLK#, CLK LVPECL output Differential clock output
[+] Feedback
P1-P3P4-P6P7-P9P10-P12

CY2XP24ZXIT

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Manufacturer:
Cypress Semiconductor
Description:
IC CLOCK 8TSSOP
Lifecycle:
New from this manufacturer.
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