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CY2XP24ZXIT

P1-P3P4-P6P7-P9P10-P12
CY2XP24
Document #: 001-15705 Rev. *G Page 4 of 12
Frequency Table
Inputs
PLL Multiplier Value Output Frequency (MHz)
Crystal Frequency (MHz) F_SEL
25 1 7.5 187.5
25 0 6.25 156.25
Absolute Maximum Conditions
Parameter Description Condition Min Max Unit
V
DD
Supply voltage – –0.5 4.4 V
V
IN
[1]
Input voltage, DC Relative to V
SS
–0.5 V
DD
+ 0.5 V
T
S
Temperature, vtorage Non operating –65 150 C
T
J
Temperature, junction – 135 C
ESD
HBM
ESD protection (human body model) JEDEC STD 22-A114-B 2000 – V
UL–94 Flammability rating At 1/8 in. V–0
JA
[2]
Thermal resistance, junction to ambient 0 m/s airflow 100 C / W
1 m/s airflow 91
2.5 m/s airflow 87
Operating Conditions
Parameter Description Min Max Unit
V
DD
3.3 V supply voltage 3.135 3.465 V
2.5 V supply voltage 2.375 2.625 V
T
A
Ambient temperature, commercial 0 70 C
Ambient temperature, industrial -40 85 C
T
PU
Power-up time for all V
DD
to reach minimum specified voltage (ensure power ramps
are monotonic)
0.05 500 ms
Note
1. The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of
copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
DC Electrical Characteristics
Parameter Description Test Conditions Min Typ Max Unit
I
DD
Power supply current with output
unterminated
V
DD
= 3.465 V, F
OUT
= 187.5 MHz,
output unterminated
––125V
V
DD
= 2.625 V, F
OUT
= 187.5 MHz,
output unterminated
––120V
I
DDT
Power supply current with output
terminated
V
DD
= 3.465 V, F
OUT
= 187.5 MHz,
output terminated
––150V
V
DD
= 2.625V, F
OUT
= 187.5 MHz,
output terminated
––145V
V
OH
LVPECL output high voltage V
DD
= 3.3 V or 2.5 V, R
TERM
= 50 to
V
DD
– 2.0 V
V
DD
–1.15 – V
DD
–0.75 V
V
OL
LVPECL output low voltage V
DD
= 3.3 V or 2.5 V, R
TERM
= 50 to
V
DD
– 2.0 V
V
DD
–2.0 – V
DD
–1.625 V
V
OD1
LVPECL Peak-to-peak output
voltage swing
V
DD
= 3.3 V or 2.5 V, R
TERM
= 50 to
V
DD
– 2.0 V
600 – 1000 mV
[+] Feedback
CY2XP24
Document #: 001-15705 Rev. *G Page 5 of 12
V
OD2
LVPECL output voltage swing
(V
OH
- V
OL
)
V
DD
= 2.5 V, R
TERM
= 50 to
V
DD
– 1.5 V
500 – 1000 mV
V
OCM
LVPECL output common mode
voltage (V
OH
+ V
OL
)/2
V
DD
= 2.5 V, R
TERM
= 50 to
V
DD
– 1.5 V
1.2 – – V
V
IH
Input high voltage 0.7 x V
DD
–V
DD
+ 0.3 V
V
IL
Input low voltage –0.3 – 0.3 x V
DD
V
I
IH
Input high current F_SEL = V
DD
––115µA
I
IL
Input low current F_SEL = V
SS
–50 – – µA
C
IN
[3]
Input capacitance, F_SEL – 15 – pF
C
INX
[3]
Pin capacitance, XIN & XOUT – 4.5 – pF
DC Electrical Characteristics (continued)
Parameter Description Test Conditions Min Typ Max Unit
AC Electrical Characteristics
[4]
Parameter Description Conditions Min Typ Max Unit
F
OUT
Output frequency 156.25 – 187.5 MHz
T
R
, T
F
[5]
Output rise/fall time 20 % to 80 % of full swing – 0.5 1.0 ns
T
Jitter()
[6]
RMS phase jitter (random) 156.25 MHz, (1.875 – 20 MHz), 3.3 V – 0.33 – ps
156.25 MHz, (12 kHz – 20 MHz), 3.3 V – 0.6 – ps
T
DC
[7]
Duty cycle Measured at zero crossing point 45 – 55 %
T
LOCK
Startup time Time for CLK to reach valid frequency
measured from the time
V
DD
= V
DD
(min.)
–– 5 ms
T
LFS
Re-lock time Time for CLK to reach valid frequency
from F_SEL pin change
–– 1 ms
Recommended Crystal Specifications
[7]
Parameter Description Min Max Unit
Mode Mode of oscillation Fundamental
F Frequency 25 25 MHz
ESR Equivalent series resistance – 50
C
0
Shunt capacitance – 7 pF
[+] Feedback
CY2XP24
Document #: 001-15705 Rev. *G Page 6 of 12
Parameter Measurements
Figure 2. 3.3 V Output Load AC Test Circuit
Figure 3. 2.5 V Output Load AC Test Circuit
Figure 4. Output DC Parameters
Figure 5. Output Rise and Fall Time
Figure 6. RMS Phase Jitter
SCOPE
V
DD
V
SS
LVPECL
50
50
Z = 50
Z = 50
CLK#
CLK
2V
-1.3V +/- 0.165V
SCOPE
V
DD
V
SS
LVPECL
50
50
Z = 50
Z = 50
CLK#
CLK
2V
-0.5V +/- 0.125V
CLK
V
A
V
B
CLK#
V
OD
V
OCM
= (V
A
+ V
B
)/2
20%
80%
T
R
CLK
20%
80%
CLK#
T
F
Phase noise
Phase noise mark
Off set Frequency
f1
f2
RMS Jitt er =
Area Under the Masked Phase Noise Plot
Noise Power
[+] Feedback
P1-P3P4-P6P7-P9P10-P12

CY2XP24ZXIT

Mfr. #:
Buy CY2XP24ZXIT
Manufacturer:
Cypress Semiconductor
Description:
IC CLOCK 8TSSOP
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