PDF: 09005aef818e3e75/Source: 09005aef818e3df5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
htf5c32x72k.fm - Rev. B 2/07 EN
9 ©2005 Micron Technology, Inc. All rights reserved.
256MB: (x72, SR) 244-Pin DDR2 Mini-RDIMM
Electrical Specifications
IDD Specifications
Tab le 8: DD R2 IDD Specifications and Conditions – 256MB
Values shown for MT47H32M16 DDR2 SDRAM only and are computed from values specified in the
512Mb (32 Meg x 16) component data sheet
Parameter/Condition Symbol -667 -53E -40E Units
Operating one bank active-precharge current:
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RAS =
t
RAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
IDD0 600 550 550 mA
Operating one bank active-read-precharge current: I
OUT = 0mA; BL = 4,
CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RAS =
t
RAS MIN (IDD),
t
RCD =
t
RCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data pattern is same as I
DD4W
I
DD1 750 675 650 mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK (IDD); CKE
is LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
I
DD2P 35 35 35 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data
bus inputs are floating
IDD2Q 275 225 200 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
IDD2N 300 250 225 mA
Active power-down current: All device banks open;
t
CK =
t
CK (IDD); CKE is LOW; Other control and address bus
inputs are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
I
DD3P 175 150 125 mA
Slow PDN exit
MR[12] = 1
60 60 60 mA
Active standby current: All device banks open;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Other control and address bus inputs are switching; Data bus
inputs are switching
I
DD3N 350 300 250 mA
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
I
DD4W 1,250 1,025 800 mA
Operating burst read current: All device banks open; Continuous burst
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
I
DD4R 1,175 975 775 mA
Burst refresh current:
t
CK =
t
CK (IDD); REFRESH command at every
t
RFC (IDD)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
I
DD5 925 875 850 mA
Self refresh current: CK and CK# at 0V; CKE ≤0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
I
DD6353535mA
Operating bank interleave read current: All device banks interleaving
reads; I
OUT = 0mA; BL = 4, CL = CL (IDD), AL =
t
RCD (IDD) - 1 x
t
CK (IDD);
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RRD =
t
RRD (IDD),
t
RCD =
t
RCD (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
I
DD7 1,750 1,700 1,700 mA