FDD107AN06LA0

©2004 Fairchild Semiconductor Corporation FDD107AN06LA0 Rev. A1
FDD107AN06LA0
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
JM
, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
DM
, in an
application. Therefore the application’s ambient
temperature, T
A
(
o
C), and thermal resistance R
θJA
(
o
C/W)
must be reviewed to ensure that T
JM
is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of P
DM
is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
θJA
for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
(EQ. 1)
P
DM
T
JM
T
A
()
R
θJA
-----------------------------=
Area in Inches Squared
(EQ. 2)
R
θJA
33.32
23.84
0.268 Area+()
--------- ----------------------------+
=
(EQ. 3)
R
θJA
33.32
154
1.73 Area+()
--------- -------------------------+
=
Area in Centimeters Squared
25
50
75
100
125
0.01 0.1 1 10
(0.645) (6.45) (64.5)(0.0645)
Figure 21. Thermal Resistance vs Mounting
Pad Area
R
θJA
= 33.32+ 23.84/(0.268+Area) EQ.2
R
θJA
(
o
C/W)
AREA, TOP COPPER AREA in
2
(cm
2
)
R
θJA
= 33.32+ 154/(1.73+Area) EQ.3
©2004 Fairchild Semiconductor Corporation FDD107AN06LA0 Rev. A1
FDD107AN06LA0
PSPICE Electrical Model
.SUBCKT FDD106AN06LA0 2 1 3 ; rev March 2002
Ca 12 8 3.5e-10
Cb 15 14 2.5e-10
Cin 6 8 3.4e-9
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 65.8
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 4.86e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 4.57e-9
RLgate 1 9 48.6
RLdrain 2 5 10
RLsource 3 7 45.7
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 24.5e-3
Rgate 9 20 3.53
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 37.5e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),2.5))}
.MODEL DbodyMOD D (IS=9.3E-13 RS=10.7e-3 IKF=0.5 TRS1=1e-4 TRS2=9e-7
+ CJO=1.55e-10 M=0.55 TT=1.6e-8 XTI=2.0)
.MODEL DbreakMOD D (RS=1.1 TRS1=2.4e-3 TRS2=-2.0e-5)
.MODEL DplcapMOD D (CJO=1.14e-10 IS=1e-30 N=10 M=0.58)
.MODEL MmedMOD NMOS (VTO=2.05 KP=2.2 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.53 T_ABS=25)
.MODEL MstroMOD NMOS (VTO=2.48 KP=15 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25)
.MODEL MweakMOD NMOS (VTO=1.75 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=35.3 RS=0.1 T_ABS=25)
.MODEL RbreakMOD RES (TC1=1.0e-3 TC2=-8.5e-7)
.MODEL RdrainMOD RES (TC1=1.0e-2 TC2=3.7e-5)
.MODEL RSLCMOD RES (TC1=4.5e-3 TC2=6.5e-6)
.MODEL RsourceMOD RES (TC1=7.0e-3 TC2=1.0e-6)
.MODEL RvthresMOD RES (TC1=-2.8e-3 TC2=-5.0e-6)
.MODEL RvtempMOD RES (TC1=-2.0e-3 TC2=1.0e-7)
MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6.0 VOFF=-3.0)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.0 VOFF=-6.0)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.4 VOFF=0.3)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.4)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
18
22
+
-
6
8
+
-
5
51
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
©2004 Fairchild Semiconductor Corporation FDD107AN06LA0 Rev. A1
FDD107AN06LA0
SABER Electrical Model
rev March 2002
template FDD106AN06LA0 n2,n1,n3 = m_temp
number m_temp=25
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=9.3e-13,rs=10.7e-3,ikf=0.5,trs1=1e-4,trs2=9e-7,cjo=1.55e-10,m=0.55,tt=1.6e-8,xti=2.0)
dp..model dbreakmod = (rs=1.1,trs1=2.4e-3,trs2=-2e-5)
dp..model dplcapmod = (cjo=1.14e-10,isl=10e-30,nl=10,m=0.58)
m..model mmedmod = (type=_n,vto=2.05,kp=2.2,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.48,kp=15,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.75,kp=0.05,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-6.0,voff=-3.0)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.0,voff=-6.0)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.4,voff=0.3)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.4)
c.ca n12 n8 = 3.5e-10
c.cb n15 n14 = 2.5e-10
c.cin n6 n8 = 3.4e-9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 65.8
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 4.86e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 4.57e-9
res.rlgate n1 n9 = 48.6
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 45.7
m.mmed n16 n6 n8 n8 = model=mmedmod, temp=m_temp, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, temp=m_temp, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, temp=m_temp, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=1.0e-3,tc2=-8.5e-7
res.rdrain n50 n16 = 24.5e-3, tc1=1.0e-2,tc2=3.7e-5
res.rgate n9 n20 = 3.53
res.rslc1 n5 n51 = 1e-6, tc1=4.5e-3,tc2=6.5e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 37.5e-3, tc1=7e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-2.8e-3,tc2=-5.0e-6
res.rvtemp n18 n19 = 1, tc1=-2.0e-3,tc2=1e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 2.5))
}
}
18
22
+
-
6
8
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6

FDD107AN06LA0

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
MOSFET N-CH 60V 10.9A D-PAK
Lifecycle:
New from this manufacturer.
Delivery:
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