LTC1069-1
6
10691fa
PIN FUNCTIONS
AGND (Pin 1): Analog Ground. The quality of the analog
signal ground can affect the fi lter performance. For either
single or dual supply operation, an analog ground plane
surrounding the package is recommended. The analog
ground plane should be connected to any digital ground
at a single point. For dual supply operation Pin 1 should
be connected to the analog ground plane.
For single supply operation Pin 1 should be bypassed to
the analog ground plane with a 0.47μF or larger capaci-
tor. An internal resistive divider biases Pin 1 to 1/2 the
total power supply. Pin 1 should be buffered if used to
bias other ICs. Figure 1 shows the connections for single
supply operation.
V
+
, V
–
(Pins 2, 7): Power Supply Pins. The V
+
(Pin 2) and
the V
–
(Pin 7) should be bypassed with a 0.1μF capacitor
to an adequate analog ground. The fi lter’s power supplies
should be isolated from other digital or high voltage analog
supplies. A low noise linear supply is recommended. Using
switching power supplies will lower the signal-to-noise
ratio of the fi lter. Unlike previous monolithic fi lters, the
power supplies can be applied at any order, that is, the
positive supply can be applied before the negative supply
and vice versa. Figure 2 shows the connection for dual
supply operation.
NC (Pins 3, 6): No Connection. Pins 3 and 6 are not con-
nected to any internal circuity; they should be preferably
tied to ground.
V
IN
(Pin 4): Filter Input Pin. The fi lter input pin is internally
connected to the inverting input of an op amp through a
43k resistor.
CLK (Pin 5): Clock Input Pin. Any TTL or CMOS clock source
with a square wave output and 50% duty cycle (±10%) is
an adequate clock source for the device. The power supply
for the clock source should not necessarily be the fi lter’s
power supply. The analog ground of the fi lter should be
connected to clock’s ground at a single point only. Table 1
shows the clock’s low and high level threshold value for a
dual or a single supply operation. A pulse generator can be
used as a clock source provided the high level ON time is
greater than 0.42μs (V
S
= ±5V). Sine waves less than 100kHz
are not recommended for clock signal because excessive
slow clock rise or fall times generate internal clock jitter.
The maximum clock rise or fall is 1μs. The clock signal
should be routed from the right side of the IC package to
avoid coupling into any input or output analog signal path.
A 1k resistor between the clock source and the clock input
pin (5) will slow down the rise and fall times of the clock
to further reduce charge coupling, Figure 1.
Table 1. Clock Source High and Low Thresholds
POWER SUPPLY HIGH LEVEL LOW LEVEL
Dual Supply = ±5V 1.5V 0.5V
Single Supply = 10V 6.5V 5.5V
Single Supply = 5V 1.5V 0.5V
Single Supply = 3.3V 1.2V 0.5V
V
OUT
(Pin 8): Filter Output Pin. Pin 8 is the output of the
fi lter and it can source or sink 1mA. Driving coaxial cables
or resistive loads less than 20k will degrade the total har-
monic distortion of the fi lter. When evaluating the device’s
dynamic range, a buffer is required to isolate the fi lter’s
output from coax cables and instruments.
Figure 1. Connections for Single Supply Operation Figure 2. Connections for Dual Supply Operation
1
2
3
4
8
7
6
5
V
OUT
V
–
NC
CLK
AGND
V
+
NC
V
IN
V
+
0.1μF
0.47μF
V
IN
10691 F01
V
OUT
1k
LTC1069-1
ANALOG GROUND PLANE
DIGITAL
GROUND
PLANE
STAR
SYSTEM
GROUND
CLOCK
SOURCE
1
2
3
4
8
7
6
5
V
OUT
V
–
NC
CLK
AGND
V
+
NC
V
IN
V
+
V
–
0.1μF 0.1μF
V
IN
V
OUT
1k
LTC1069-1
ANALOG GROUND PLANE
DIGITAL
GROUND
PLANE
STAR
SYSTEM
GROUND
CLOCK
SOURCE
10691 F02
