9397 750 15123 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 13 June 2005 10 of 18
Philips Semiconductors
74ALVT16821
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
[5] This parameter is valid for any V
CC
between 0 V and 1.2 V with a transition time of up to 10 ms. From V
CC
= 1.2 V to (2.5 ± 0.2) V
a transition time of 100 µs is permitted. This parameter is valid for T
amb
=25°C only.
[6] I
CC
is measured with outputs pulled up to V
CC
or pulled down to ground.
[7] This is the increase in supply current for each input at the specified voltage level other than V
CC
or GND.
[8] All typical values are measured at V
CC
= 3.3 V and T
amb
= 25 °C.
[9] This parameter is valid for any V
CC
between 0 V and 1.2 V with a transition time of up to 10 ms. From V
CC
= 1,2 V to (3.3 ± 0.3) V
a transition time of 100 µs is permitted. This parameter is valid for T
amb
=25°C only.
11. Dynamic characteristics
[1] All typical values are measured at V
CC
= 2.5 V and T
amb
= 25 °C.
[2] All typical values are measured at V
CC
= 3.3 V and T
amb
= 25 °C.
Table 8: Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
T
amb
=
−
40
°
C to +85
°
C.
Symbol Parameter Conditions Min Typ Max Unit
V
CC
= 2.5 V ± 0.2 V
[1]
t
PLH
propagation delay nCP to nQx see Figure 5 1.0 2.6 4.0 ns
t
PHL
propagation delay nCP to nQx see Figure 5 1.0 2.7 4.4 ns
t
PZH
output enable time nOE to nQx see Figure 7 1.5 2.8 4.6 ns
t
PZL
output enable time nOE to nQx see Figure 8 1.0 1.8 4.1 ns
t
PHZ
output disable time nOE to nQx see Figure 7 1.5 2.7 4.4 ns
t
PLZ
output disable time nOE to nQx see Figure 8 1.0 2.1 3.3 ns
t
su(H)
set-up time HIGH nDx to nCP see Figure 6 1.5 0.1 - ns
t
su(L)
set-up time LOW nDx to nCP see Figure 6 2.0 0.5 - ns
t
h(H)
hold time HIGH nDx to nCP see Figure 6 0.3 −0.5 - ns
t
h(L)
hold time LOW nDx to nCP see Figure 6 0.5 −0.1 ns
t
WH
nCP pulse width HIGH see Figure 5 1.5 - - ns
t
WL
nCP pulse width LOW see Figure 5 1.5 - - ns
f
max
maximum clock frequency see Figure 5 150 - - MHz
V
CC
= 3.3 V ± 0.3 V
[2]
t
PLH
propagation delay nCP to nQx see Figure 5 0.5 1.7 3.0 ns
t
PHL
propagation delay nCP to nQx see Figure 5 0.5 1.8 3.2 ns
t
PZH
output enable time nOE to nQx see Figure 7 1.0 2.1 3.5 ns
t
PZL
output enable time nOE to nQx see Figure 8 0.5 1.4 3.0 ns
t
PHZ
output disable time nOE to nQx see Figure 7 1.5 2.9 4.2 ns
t
PLZ
output disable time nOE to nQx see Figure 8 1.5 2.4 3.4 ns
t
su(H)
set-up time HIGH nDx to nCP see Figure 6 1.5 0.1 - ns
t
su(L)
set-up time LOW nDx to nCP see Figure 6 1.5 0.1 - ns
t
h(H)
hold time, HIGH nDx to nCP see Figure 6 0.5 0.1 - ns
t
h(L)
hold time, LOW nDx to nCP see Figure 6 0.5 0.1 - ns
t
WH
nCP pulse width HIGH see Figure 5 1.5 - - ns
t
WL
nCP pulse width LOW see Figure 5 1.5 - - ns
f
max
maximum clock frequency see Figure 5 150 - - MHz
