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74ALVT16821DGGY

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
9397 750 15123 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 13 June 2005 12 of 18
Philips Semiconductors
74ALVT16821
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
Measurement points are given in Table 9.
V
OL
and V
OH
are typical voltage output drop that occur with the output load.
Fig 8. 3-state output enable time to LOW-level and output disable time from LOW-level
Table 9: Measurement points
Supply voltage Input Output
V
M
V
M
V
X
V
Y
≥ 3 V 1.5 V 1.5 V V
OL
+ 0.3 V V
OH
− 0.3 V
≤ 2.7 V 0.5 × V
CC
0.5 × V
CC
V
OL
+ 0.15 V V
OH
− 0.15 V
001aad161
t
PZL
t
PLZ
V
X
V
M
V
M
V
OL
V
OH
GND
V
I
output nQx
input nOE
9397 750 15123 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 13 June 2005 13 of 18
Philips Semiconductors
74ALVT16821
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
Measurement points are given in Table 9.
a. Input pulse definition
Test data is given in Table 10.
Definitions test circuit:
R
L
= Load resistor.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
V
EXT
= Test voltage for switching times.
b. Test circuit
Fig 9. Load circuitry for switching times
Table 10: Test data
Input Load V
EXT
V
I
f
i
t
W
t
r
, t
f
C
L
R
L
t
PLZ
, t
PZL
t
PLH
, t
PHL
t
PHZ
,t
PZH
3.0 V or V
CC
whichever is
less
≤ 10 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω 6 V or
2 × V
CC
open GND
001aac221
V
M
V
M
t
W
t
W
10 %
90 % 90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 % 10 %
t
THL
(t
f
)
t
TLH
(t
r
)
t
TLH
(t
r
)
t
THL
(t
f
)
V
EXT
V
CC
V
I
V
O
mna616
DUT
C
L
R
T
R
L
R
L
PULSE
GENERATOR
9397 750 15123 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 03 — 13 June 2005 14 of 18
Philips Semiconductors
74ALVT16821
20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
13. Package outline
Fig 10. Package outline SOT371-1 (SSOP56)
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.4
0.2
2.35
2.20
0.25
0.3
0.2
0.22
0.13
18.55
18.30
7.6
7.4
0.635
10.4
10.1
1.0
0.6
1.2
1.0
0.85
0.40
8
0
o
o
0.180.251.4 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT371-1
99-12-27
03-02-18
(1)
w M
b
p
D
H
E
E
Z
e
c
v M
A
X
A
y
56
29
MO-118
28
1
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
pin 1 index
0 5 10 mm
scale
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
A
max.
2.8
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

74ALVT16821DGGY

Mfr. #:
Buy 74ALVT16821DGGY
Manufacturer:
Nexperia
Description:
Flip Flops 20-Bit Bus-Interface D-Type Flip-Flop
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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