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8N3Q001KG-0032CDI8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
13 ©2012 Integrated Device Technology, Inc.
Schematic Layout
Figure 3 shows an example of IDT8N3Q001 application schematic.
In this example, the device is operated at V
CC
= 3.3V. As with any
high speed analog circuitry, the power supply pins are vulnerable to
noise. To achieve optimum jitter performance, power supply isolation
is required. The IDT8N3Q001 provides separate power supplies to
isolate from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
Figure 3. IDT8N3Q001 Application Schematic
Zo = 50 Ohm
nQ
R7
50
RU2
Not Install
SC LK
R3
133
SD AT A
Logic Control Input Examples
FSEL1
R1
SP
VC C
+
-
BLM1 8BB221SN 1
Ferrite Bead
1 2
RU1
1K
RD1
Not Install
Q
VCC
3.3V
R2
SP
R6
82.5
C3
0. 1uF
VCC
OE
3.3V
To Logic
Input
pins
Set Logic
Input to
'0'
FSEL0
R4
133
VCC
Zo = 50 Ohm
R9
50
R5
82. 5
C1
0. 1uF
Optional
Y-Termination
R8
50
To Logic
Input
pins
C2
10uF
Set Logic
Input to
'1'
Zo = 50 Ohm
U1
1
2
3 6
7
8
4
5 9
10
DNU
OE
VEE Q
nQ
VCC
FSEL0
FSEL1 SDATA
SCLK
VCC=3.3V
+
-
RD2
1K
Zo = 50 Ohm
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
14 ©2012 Integrated Device Technology, Inc.
Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8N3Q001.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the IDT8N3Q001 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 140mA = 485.1mW
• Power (outputs)
MAX
= 34.2mW/Loaded Output pair
Total Power_
MAX
(3.465V, with all outputs switching) = 485.1mW + 34.2mW = 519.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 49.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.519W * 49.4°C/W = 110.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance
JA
for 10 Lead Ceramic 5mm x 7mm Package, Forced Convection
JA
by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 49.4°C/W 44.2°C/W 41°C/W
IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
IDT8N3Q001GCD REVISION A
MARCH 6, 2012
15 ©2012 Integrated Device Technology, Inc.
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 4.
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
V
CC
– 2V.
• For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
– 0.8V
(V
CC_MAX
– V
OH_MAX
) = 0.8V
• For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
– 1.5V
(V
CC_MAX
– V
OL_MAX
) = 1.5V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OH_MAX
) = [(2V – (V
CC_MAX
– V
OH_MAX
))/R
L
] * (V
CC_MAX
– V
OH_MAX
) =
[(2V – 0.8V)/50] * 0.8V = 19.2mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OL_MAX
) = [(2V – (V
CC_MAX
– V
OL_MAX
))/R
L
] * (V
CC_MAX
– V
OL_MAX
) =
[(2V – 1.5V)/50] * 1.5V = 15mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 34.2mW
V
OUT
V
CC
V
CC
- 2V
Q1
RL
50Ω
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

8N3Q001KG-0032CDI8

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