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TS2007IQT

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Application information TS2007
22/29 Doc ID 13123 Rev 4
4 Application information
4.1 Differential configuration principle
The TS2007 is a monolithic fully-differential input/output class D power amplifier. The
TS2007 also includes a common-mode feedback loop that controls the output bias value to
average it at V
CC
/2 for any DC common-mode input voltage. This allows the device to
always have a maximum output voltage swing, and by consequence, maximize the output
power. Moreover, as the load is connected differentially compared to a single-ended
topology, the output is four times higher for the same power supply voltage.
The advantages of a full-differential amplifier are:
● High PSRR (power supply rejection ratio)
● High common-mode noise rejection
● Virtually zero pop without additional circuitry, giving a faster startup time compared to
conventional single-ended input amplifiers
● Easier interfacing with differential output audio DAC
● No input coupling capacitors required thanks to common-mode feedback loop
4.2 Gain settings
In the flat region of the frequency-response curve (no input coupling capacitor or internal
feedback loop + load effect), the differential gain can be set to either 6 or 12 dB depending
on the logic level of the GS pin:
Note: Between the GS pin and V
CC
there is an internal 300 k
Ω
resistor. When the pin is floating
the gain is 6 dB.
4.3 Common-mode feedback loop limitations
As explained previously, the common-mode feedback loop allows the output DC bias
voltage to be averaged at V
CC
/2 for any DC common-mode bias input voltage.
Due to the V
ic
limitation of the input stage (see Table 2: Operating conditions on page 3), the
common-mode feedback loop can fulfill its role only within the defined range.
4.4 Low frequency response
If a low frequency bandwidth limitation is required, it is possible to use input coupling
capacitors. In the low frequency region, the input coupling capacitor C
in
starts to have an
effect. C
in
forms, with the input impedance Z
in
, a first order high-pass filter with a -3 dB cutoff
frequency (see Table 5 to Ta bl e 9 ).
GS Gain (dB) Gain (V/V)
16 dB2
0 12 dB 4
TS2007 Application information
Doc ID 13123 Rev 4 23/29
So, for a desired cutoff frequency F
CL
we can calculate C
in
:
with F
CL
in Hz, Z
in
in Ω and C
in
in F.
The input impedance Z
in
is for the whole power supply voltage range, typically 75 k
Ω
. There
is also a tolerance around the typical value (see Ta b l e 5 to Tabl e 9). With regard to the
tolerance, you can also calculate tolerance of F
CL
:
●
●
4.5 Decoupling of the circuit
A power supply capacitor, referred to as C
S,
is needed to correctly bypass the TS2007.
The TS2007 has a typical switching frequency of 280 kHz and output fall and rise time of
about 5 ns. Due to these very fast transients, careful decoupling is mandatory.
A 1 µF ceramic capacitor is enough, but it must be located very close to the TS2007 in order
to avoid any extra parasitic inductance created by a long track wire. Parasitic loop
inductance, in relation with di/dt, introduces overvoltage that decreases the global efficiency
of the device and may cause, if this parasitic inductance is too high, a TS2007 breakdown.
In addition, even if a ceramic capacitor has an adequate high frequency ESR value, its
current capability is also important. A 0603 size is a good compromise, particularly when a
4 Ω load is used.
Another important parameter is the rated voltage of the capacitor. A 1µF/6.3V capacitor
used at 5 V, loses about 50% of its value. With a power supply voltage of 5 V, the decoupling
value, instead of 1 µF, could be reduced to 0.5 µF. As C
S
has particular influence on the
THD+N in the medium to high frequency region, this capacitor variation becomes decisive.
In addition, less decoupling means higher overshoots which can be problematic if they reach
the power supply AMR value (6 V).
4.6 Wake-up time (t
wu
)
When the standby is released to set the device ON, there is a wait of 5 ms typically. The
TS2007 has an internal digital delay that mutes the outputs and releases them after this
time in order to avoid any pop noise.
Note: The gain increases smoothly (see Figure 49) from the mute to the gain selected by the GS
pin (Section 4.2).
F
CL
1
2 π Z
in
C
in
⋅⋅ ⋅
------------------------------------=
C
in
1
2 π Z
in
F
CL
⋅⋅ ⋅
--------------------------------------=
F
CLmax
1.103 F
CL
⋅=
F
CLmin
0.915 F
CL
⋅=
Application information TS2007
24/29 Doc ID 13123 Rev 4
4.7 Shutdown time
When the standby command is set, the time required to put the two output stages into high
impedance and to put the internal circuitry in shutdown mode, is typically 5 ms. This time is
used to decrease the gain and avoid any pop noise during shutdown.
Note: The gain decreases smoothly until the outputs are muted (see Figure 49).
4.8 Consumption in shutdown mode
Between the shutdown pin and GND there is an internal 300 kΩ resistor. This resistor forces
the TS2007 to be in shutdown when the shutdown input is left floating.
However, this resistor also introduces additional shutdown power consumption if the
shutdown pin voltage is not 0 V.
Referring to Table 2: Operating conditions on page 3, with a 0.4 V shutdown voltage pin for
example, you must add 0.4V/300k = 1.3 µA in typical (0.4V/273 k = 1.46 µA in maximum) to
the shutdown current specified in Ta ble 5 to Ta bl e 9.
4.9 Single-ended input configuration
It is possible to use the TS2007 in a single-ended input configuration. However, input
coupling capacitors are needed in this configuration. The following schematic diagram
shows a typical single-ended input application.
Figure 50. Typical application for single-ended input configuration
VCC
Cin
CinInput
Speaker
Cs
1uF
TS2007
Gain
Select
+
-
Standby
Control
3
4
21
5
8
67
PWM
H
Bridge
Oscillator
IN-
IN+
GS Vcc
OUT+
OUT-
Standby
Gnd
Gain Select Control
Standby Control
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TS2007IQT

Mfr. #:
Buy TS2007IQT
Manufacturer:
STMicroelectronics
Description:
Audio Amplifiers 3W filter free ClassD audio Pwr amp
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