CY7B92
CY7B93
Document #: 38-02017 Rev. *C Page 10 of 30
mode the proper sense of running disparity cannot be
guaranteed for the first pad character, but is correct for all pad
characters that follow). This automatic insertion of pad
characters can be inhibited by insuring that the Transmitter is
always enabled (i.e., ENA
or ENN is hard-wired LOW).
PECL Output Functional and Connection Options
The three pairs of PECL outputs all contain the same infor-
mation and are intended for use in systems with multiple
connections. Each output pair may be connected to a different
serial media, each of which may be a different length, link type,
or interface technology. For systems that do not require all
three output pairs, the unused pairs should be wired to V
CC
to
minimize the power dissipated by the output circuit, and to
minimize unwanted noise generation. An internal voltage
comparator detects when an output differential pair is wired to
V
CC
, causing the current source for that pair to be disabled.
This results in a power savings of around 5 mA for each
unused pair.
In systems that require the outputs to be shut off during some
periods when link transmission is prohibited (e.g., for laser
safety functions), the FOTO input can be asserted. While it is
possible to insure that the output state of the PECL drivers is
LOW (i.e., light is off) by sending all 0’s in Bypass mode, it is
often inconvenient to insert this level of control into the data
transmission channel, and it is impossible in Encoded mode.
FOTO is provided to simplify and augment this control function
(typically found in laser-based transmission systems). FOTO
will force OUTA+ and OUTB+ to go LOW, OUTA- and OUTB-
to go HIGH, while allowing OUTC± to continue to function
normally (OUTC is typically used as a diagnostic feedback and
cannot be disabled). This separation of function allows various
system configurations without undue load on the control
function or data channel logic.
Transmitter Serial Data Characteristics
The CY7B923 HOTLink Transmitter serial output conforms to
the requirements of the Fibre Channel specification. The serial
data output is controlled by an internal Phase-Locked Loop
that multiplies the frequency of CKW by ten (10) to maintain
the proper bit clock frequency. The jitter characteristics
(including both PLL and logic components) are shown below:
• Deterministic Jitter (D
j
) < 35 ps (peak-peak). Typically
measured while sending a continuous K28.5 (C5.0).
• Random Jitter (R
j
) < 175 ps (peak-peak). Typically
measured while sending a continuous K28.7 (C7.0).
Transmitter Test Mode Description
The CY7B923 Transmitter offers two types of test mode
operation, BIST mode and Test mode. In a normal system
application, the Built-In Self-Test (BIST) mode can be used to
check the functionality of the Transmitter, the Receiver, and
the link connecting them. This mode is available with minimal
impact on user system logic, and can be used as part of the
normal system diagnostics. Typical connections and timing
are shown in Figure 6.
