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BIST mode is intended to check the entire function of the
Transmitter (except the Transmitter input pins and the bypass
function in the Encoder), the serial link, and the Receiver. It
augments normal factory ATE testing and provides the
designer with a rigorous test mechanism to check the link
transmission system without requiring any significant system
overhead.
While in Bypass mode, the BIST logic will function in the same
way as in the Encoded mode. MODE = HIGH and
BISTEN
= LOW causes the Transmitter to switch to Encoded
mode and begin sending the BIST pattern, as if MODE = LOW.
When BISTEN
returns to HIGH, the Transmitter resumes
normal Bypass operation. In Test mode the BIST function
works as in the Normal mode. For more information on BIST,
consult the “HOTLink Built-In Self-Test” application note.
Test Mode
The MODE input pin selects between three transmitter
functional modes. When wired to VCC, the D(
a-j
) inputs bypass
the Encoder and load directly from the Input register into the
Shifter. When wired to GND, the inputs D
0-7
, SVS, and SC/D
are encoded using the Fibre Channel 8B/10B codes and
sequences (shown at the end of this datasheet). Since the
Transmitter is usually hard wired to Encoded or Bypass mode
and not switched between them, a third function is provided for
the MODE pin. Test mode is selected by floating the MODE
pin (internal resistors hold the MODE pin at V
CC
/2). Test mode
is used for factory or incoming device test.
Test mode causes the Transmitter to function in its Encoded
mode, but with OutA+/OutB+ (used as a differential test clock
input) as the bit rate clock input instead of the internal
PLL-generated bit clock. In this mode, inputs are clocked by
CKW and transfers between the Input register and Shifter are
timed by the internal counters. The bit-clock and CKW must
maintain a fixed phase and divide-by-ten ratio. The phase and
pulse width of RP
are controlled by phases of the bit counter
(PLL feedback counter) as in Normal mode. Input and output
patterns can be synchronized with internal logic by observing
the state of RP
or the device can be initialized to match an ATE
test pattern using the following technique:
1. With the MODE pin either HIGH or LOW, stop CKW and
bit-clock.
2. Force the MODE pin to MID (open or V
CC
/2) while the
clocks are stopped.
3. Start the bit-clock and let it run for at least two cycles.
4. Start the CKW clock at the bit-clock/10 rate.
Test mode is intended to allow logical, DC, and AC testing of
the Transmitter without requiring that the tester check output
data patterns at the bit rate, or accommodate the PLL lock,
tracking, and frequency range characteristics that are required
when the HOTLink part operates in its normal mode. To use
OutA+/OutB+ as the test clock input, the FOTO input is held
HIGH while in Test mode. This forces the two outputs to go to
an “PECL LOW,” which can be ignored while the test system
creates a differential input signal at some higher voltage.
CY7B933 HOTLink Receiver Operating Mode
Description
In normal user operation, the Receiver can operate in either of
two modes. The Encoded mode allows a user system to send
and receive eight-bit data and control information without first
converting it to transmission characters. The Bypass mode is
used for systems in which the encoding and decoding is
performed by an external protocol controller.
In either mode, serial data is received at one of the differential
line receiver inputs and routed to the Shifter and the Clock
Synchronization. The PLL in the Clock Synchronizer aligns the
internally generated bit rate clock with the incoming data
stream and clocks the data into the shifter. At the end of a byte
time (ten bit times), the data accumulated in the shifter is trans-
ferred to the Decode register.
To properly align the incoming bit stream to the intended byte
boundaries, the bit counter in the Clock Synchronizer must be
initialized. The Framer logic block checks the incoming bit
stream for the unique pattern that defines the byte boundaries.
This combinatorial logic filter looks for the X3.230 symbol
defined as “Special Character Comma” (K28.5). Once K28.5
is found, the free running bit counter in the Clock Synchronizer
block is synchronously reset to its initial state, thus “framing”
the data to the correct byte boundaries.
Since noise-induced errors can cause the incoming data to be
corrupted, and since many combinations of error and legal
data can create an alias K28.5, an option is included to disable
resynchronization of the bit counter. The Framer will be
inhibited when the RF input is held LOW. When RF rises, RDY
will be inhibited until a K28.5 has been detected, and RDY will
resume its normal function. Data will continue to flow through
the Receiver while RDY
is inhibited.
Encoded Mode Operation
In Encoded mode the serial input data is decoded into eight
bits of data (Q
0
– Q
7
), a context control bit (SC/D), and a
system diagnostic output bit (RVS). If the pattern in the
Decode register is found in the Valid Data Characters table,
the context of the data is decoded as normal message data
and the SC/D
output will be LOW. If the incoming bit pattern is
found in the Valid Special Character Codes and Sequences
table, it is interpreted as “control” or “protocol information,” and
the SC/D
output will be HIGH. Special characters include all
protocol characters defined for use in packets for Fibre
Channel, ESCON, and other proprietary and diagnostic
purposes.
The Violation symbol that can be explicitly sent as part of a
user data packet (i.e., Transmitter sending C0.7; D
7-0
= 111
00000 and SC/D
= 1; or SVS = 1) will be decoded and
indicated in exactly the same way as a noise-induced error in
the transmission link. This function will allow system
diagnostics to evaluate the error in an unambiguous manner,
and will not require any modification to the receiver data
interface for error-testing purposes.
Bypass Mode Operation
In Bypass mode the serial input data is not decoded, and is
transferred directly from the Decode register to the Output
register’s 10 bits (Q(
a-j
). It is assumed that the data has been
preencoded prior to transmission, and will be decoded in
subsequent logic external to HOTLink. This data can use any
encoding method suitable to the designer. The only restrictions
upon the data encoding method is that it contain suitable
transition density for the Receiver PLL data synchronizer (one
per 10 bit byte) and that it be compatible with the transmission
media.
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The framer function in Bypass mode is identical to Encoded
mode, so a K28.5 pattern can still be used to reframe the serial
bit stream.
Parallel Output Function
The 10 outputs (Q
0-7
, SC/D, and RVS) all transition simulta-
neously, and are aligned with RDY
and CKR with timing allowances
to interface directly with either an asynchronous FIFO or a clocked
FIFO. Typical FIFO connections are shown in Figure 4.
Data outputs can be clocked into the system using either the
rising or falling edge of CKR, or the rising or falling edge of
RDY
. If CKR is used, RDY can be used as an enable for the
receiving logic. A LOW pulse on RDY
shows that new data has
been received and is ready to be delivered. The signal on RDY
is a 60%-LOW duty cycle byte-rate pulse train suitable for the
write pulse in asynchronous FIFOs such as the CY7C42X, or
the enable write input on Clocked FIFOs such as the
CY7C44X. HIGH on RDY
shows that the received data
appearing at the outputs is the null character (normally
inserted by the transmitter as a pad between data inputs) and
should be ignored.
When the Transmitter is disabled it will continuously send pad
characters (K28.5). To assure that the receive FIFO will not be
overfilled with these dummy bytes, the RDY
pulse output is
inhibited during fill strings. Data at the Q
0-7
outputs will reflect the
correct received data, but will not appear to change, since a string
of K28.5s all are decoded as Q7-0 =000 00101 and SC/D
= 1
(C5.0). When new data appears (not K28.5), the RDY
output will
resume normal function. The “last” K28.5 will be accompanied by a
normal RDY
pulse.
Fill characters are defined as any K28.5 followed by another
K28.5. All fill characters will not cause RDY to pulse. Any
K28.5 followed by any other character (including violation or
illegal characters) will be interpreted as usable data and will
cause RDY
to pulse.
As noted above, RDY
can also be used as an indication of correct
framing of received data. While the Receiver is awaiting receipt of a
K28.5 with RF HIGH, the RDY
outputs will be inhibited. When RDY
resumes, the received data will be properly framed and will be
decoded correctly. In Bypass mode with RF HIGH, RDY will pulse
once for each K28.5 received. For more information on the RDY
pin, consult the “HOTLink CY7B933 RDY Pin Description” appli-
cation note.
Code rule violations and reception errors will be indicated as
follows:
RVS
SC/D Qouts Name
1. Good Data code received
with good running disparity (RD)0000-FFD0.0-31.7
2. Good Special Character
code received with good RD 0 1 00-0B C0.0-11.0
3. K28.7 immediately following
K28.1 (ESCON Connect_SOF)0 1 27 C7.1
4. K28.7 immediately following
K28.5 (ESCON Passive_SOF) 0147 C7.2
5. Unassigned code received 1 1 E0 C0.7
6. -K28.5+ received when
RD was + 1 1 E1 C1.7
7. +K28.5- received when
RD was - 1 1 E2 C2.7
8. Good code received
with wrong RD 1 1 E4 C4.7
Receiver Serial Data Requirements
The CY7B933 HOTLink Receiver serial input capability
conforms to the requirements of the Fibre Channel specifi-
cation. The serial data input is tracked by an internal PLL that
is used to recover the clock phase and to extract the data from
the serial bit stream. Jitter tolerance characteristics (including
both PLL and logic component requirements) are shown
below:
Deterministic Jitter Tolerance (Dj) > 40% of tB. Typically
measured while receiving data carried by a
bandwidth-limited channel (e.g., a coaxial transmission line)
while maintaining a Bit Error Rate (BER) < 10–12.
Random Jitter Tolerance (Rj) > 90% of tB. Typically
measured while receiving data carried by a
random-noise-limited channel (e.g., a fiber-optic trans-
mission system with low light levels) while maintaining a Bit
Error Rate (BER) < 10–12.
Total Jitter Tolerance > 90% of tB. Total of Dj + Rj.
PLL-Acquisition Time < 500-bit times from worst-case
phase or frequency change in the serial input data stream,
to receiving data within BER objective of 10-12. Stable
power supplies within specifications, stable REFCLK input
frequency and normal data framing protocols are assumed.
Note: Acquisition time is measured from worst-case phase
or frequency change to zero phase and frequency error. As
a result of the receiver’s wide jitter tolerance, valid data will
appear at the receiver’s outputs a few byte times after a
worst-case phase change.
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Receiver Test Mode Description
The CY7B933 Receiver offers two types of test mode
operation, BIST mode and Test mode. In a normal system
application, the Built-In Self-Test (BIST) mode can be used to
check the functionality of the Transmitter, the Receiver and the
link connecting them. This mode is available with minimal
impact on user system logic, and can be used as part of the
normal system diagnostics. Typical connections and timing
are shown in Figure 6.
BIST Mode
BIST Mode function is as follows:
1. Set BISTEN
LOW to enable self-test generation and await
RDY
LOW indicating that the initialization code has been
received.
2. Monitor RVS and check for any byte time with the pin HIGH
to detect pattern mismatches. RDY
will pulse HIGH once
per BIST loop, and can be used by an external counter to
monitor test pattern progress. Q
0-7
and SC/D will show the
expected pattern and may be useful for debug purposes.
3. When testing is completed, set BISTEN
HIGH and resume
normal function.
Note: A specific test of the RVS output may be required to
assure an adequate test. To perform this test, it is only
necessary to have the Transmitter send violation (SVS =
HIGH) for a few bytes before beginning the BIST test
sequence. Alternatively, the Receiver could enter BIST mode
after the Transmitter has begun sending BIST loop data, or be
removed before the Transmitter finishes sending BIST loops,
each of which contain several deliberate violations and should
cause RVS to pulse HIGH.
BIST mode is intended to check the entire function of the
Transmitter, serial link, and Receiver. It augments normal
factory ATE testing and provides the user system with a
rigorous test mechanism to check the link transmission
system, without requiring any significant system overhead.
When in Bypass mode, the BIST logic will function in the same
way as in the Encoded mode. MODE = HIGH and BISTEN
=
LOW causes the Receiver to switch to Encoded mode and begin
checking the decoded received data of the BIST pattern, as if
MODE = LOW. When BISTEN
returns to HIGH, the Receiver
resumes normal Bypass operation. In Test mode the BIST function
works as in the normal mode.
Test Mode
The MODE input pin selects between three receiver functional
modes. When wired to VCC, the Shifter contents bypass the
Decoder and go directly from the Decoder latch to the Q
a-j
inputs of
the Output latch. When wired to GND, the outputs are decoded
using the 8B/10B codes shown at the end of this datasheet and
become Q
0-7
, RVS, and SC/D. The third function is Test mode,
used for factory or incoming device test. This mode can be selected
by leaving the MODE pin open (internal circuitry forces the open pin
to VCC/2).
Test mode causes the Receiver to function in its Encoded
mode, but with INB (INB+) as the bit rate Test clock instead of
the Internal PLL generated bit clock. In this mode, transfers
between the Shifter, Decoder register and Output register are
controlled by their normal logic, but with an external bit rate
clock instead of the PLL (the recovered bit clock). Internal logic
and test pattern inputs can be synchronized by sending a
SYNC pattern and allowing the Framer to align the logic to the
bit stream. The flow is as follows:
1. Assert Test mode for several test clock cycles to establish
normal counter sequence.
2. Assert RF to enable reframing.
3. Input a repeating sequence of bits representing K28.5
(Sync).
4. RDY
falling shows the byte boundary established by the
K28.5 input pattern.
5. Proceed with pattern, voltage and timing tests as is conve-
nient for the test program and tester to be used.
(While in Test mode and in BIST mode with RF HIGH, the Q
0-7
,
RVS, and SC/D
outputs reflect various internal logic states and not
the received data.)
Test mode is intended to allow logical, DC, and AC testing of
the Receiver without requiring that the tester generate input
data at the bit rate or accommodate the PLL lock, tracking and
frequency range characteristics that are required when the
part operates in its normal mode.
X3.230 Codes and Notation Conventions
Information to be transmitted over a serial link is encoded eight
bits at a time into a 10-bit Transmission Character and then
sent serially, bit by bit. Information received over a serial link
is collected ten bits at a time, and those Transmission
Characters that are used for data (Data Characters) are
decoded into the correct eight-bit codes. The 10-bit Trans-
mission Code supports all 256 8-bit combinations. Some of the
remaining Transmission Characters (Special Characters) are
used for functions other than data transmission.
The primary rationale for use of a Transmission Code is to
improve the transmission characteristics of a serial link. The
encoding defined by the Transmission Code ensures that suffi-
cient transitions are present in the serial bit stream to make
clock recovery possible at the Receiver. Such encoding also
greatly increases the likelihood of detecting any single or
multiple bit errors that may occur during transmission and
reception of information. In addition, some Special Characters
of the Transmission Code selected by Fibre Channel Standard
consist of a distinct and easily recognizable bit pattern (the
Special Character Comma) that assists a Receiver in
achieving word alignment on the incoming bit stream.
Notation Conventions
The documentation for the 8B/10B Transmission Code uses
letter notation for the bits in an 8-bit byte. Fibre Channel
Standard notation uses a bit notation of A, B, C, D, E, F, G, H
for the 8-bit byte for the raw 8-bit data, and the letters a, b, c,
d, e, i, f, g, h, j for encoded 10-bit data. There is a correspon-
dence between bit A and bit a, B and b, C and c, D and d, E
and e, F and f, G and g, and H and h. Bits i and j are derived,
respectively, from (A,B,C,D,E) and (F,G,H).
The bit labeled A in the description of the 8B/10B Transmission
Code corresponds to bit 0 in the numbering scheme of the
FC-2 specification, B corresponds to bit 1, as shown below.
FC-2 bit designation 76543210
HOTLink D/Q designation76543210
8B/10B bit designation— H G F E D C B A

CY7B923-SC

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IC TXRX FIBRE CHAN 28SOIC
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