CY7B92
CY7B93
Document #: 38-02017 Rev. *C Page 25 of 30
Transmitter Switching Characteristics Over the Operating Range
[7]
Parameter Description
7B923-155 7B923 7B923-400
UnitMin. Max Min. Max Min. Max
t
CKW
Write Clock Cycle 62.5 66.7 30.3 62.5 25 62.5 ns
t
B
Bit Time
[15]
6.25 6.67 3.03 6.25 2.5 6.25 ns
t
CPWH
CKW Pulse Width HIGH 6.5 6.5 6.5 ns
t
CPWL
CKW Pulse Width LOW 6.5 6.5 6.5 ns
t
SD
Data Set-Up Time
[16]
5 5 5 ns
t
HD
Data Hold Time
[16]
0 0 0 ns
t
SENP
Enable Set-Up Time (to insure correct RP)
[17]
6t
B
+ 8 6t
B
+ 8 6t
B
+ 8 ns
t
HENP
Enable Hold Time (to insure correct RP)
[17]
0 0 0 ns
t
PDR
Read Pulse Rise Alignment
[18]
–4 2 –4 2 –4 2 ns
t
PPWH
Read Pulse HIGH
[18]
4t
B
–3 4t
B
–3 4t
B
–3 ns
t
PDF
Read Pulse Fall Alignment
[18]
6t
B
–3 6t
B
–3 6t
B
–3 ns
t
RISE
PECL Output Rise Time 20−80% (PECL Test Load)
[13]
1.2 1.2 1.2 ns
t
FALL
PECL Output Fall Time 80−20% (PECL Test Load)
[13]
1.2 1.2 1.2 ns
t
DJ
Deterministic Jitter (peak-peak)
[13, 19]
35 35 35 ps
t
RJ
Random Jitter (peak-peak)
[13, 20]
175 175 175 ps
t
RJ
Random Jitter (σ)
[13,20]
20 20 20 ps
Receiver Switching Characteristics Over the Operating Range
[7]
Parameter Description
7B933-155 7B933 7B933-400
UnitMin. Max Min. Max. Min. Max.
t
CKR
Read Clock Period (No Serial Data Input), REFCLK
as Reference
[21]
–1 +1 –1 +1 –1 +1 %
t
B
Bit Time
[22]
6.25 6.67 3.03 6.25 2.5 6.25 ns
t
CPRH
Read Clock Pulse HIGH 5t
B
–3 5t
B
–3 5t
B
–3 ns
t
CPRL
Read Clock Pulse LOW 5t
B
–3 5t
B
–3 5t
B
–3 ns
t
RH
RDY Hold Time t
B
–2.5 t
B
–2.5 t
B
–2.5 ns
t
PRF
RDY Pulse Fall to CKR Rise 5t
B
–3 5t
B
–3 5t
B
–3 ns
t
PRH
RDY Pulse Width HIGH 4t
B
–3 4t
B
–3 4t
B
–3 ns
t
A
Data Access Time
[23, 24]
2t
B
–2 2t
B
+4 2t
B
–2 2t
B
+4 2t
B
–2 2t
B
+4 ns
t
ROH
Data Hold Time
[23, 24]
t
B
–2.5 t
B
–2.5 t
B
–2.5 ns
t
H
Data Hold Time from CKR Rise
[23, 24]
2t
B
–3 2t
B
–3 2t
B
–3 ns
t
CKX
REFCLK Clock Period Referenced to CKW of Trans-
mitter
[25]
–0.1 +0.1 –0.1 +0.1 –0.1 +0.1 %
Notes:
15. Transmitter t
B
is calculated as t
CKW
/10. The byte rate is one tenth of the bit rate.
16. Data includes D
0−7
, SC/D, SVS, ENA, ENN, and BISTEN. t
SD
and t
HD
minimum timing assures correct data load on rising edge of CKW, but not RP function or timing.
17. t
SENP
and t
HENP
timing insures correct RP function and correct data load on the rising edge of CKW.
18. Loading on RP
is the standard TTL test load shown in part (a) of AC Test Loads and Waveforms except C
L
= 15 pF.
19. While sending continuous K28.5s, RP
unloaded, outputs loaded to 50Ω to V
CC
−2.0V, over the operating range.
20. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to CKW input, over the operating
range.
21. The period of t
CKR
will match the period of the transmitter CKW when the receiver is receiving serial data. When data is interrupted, CKR may drift to one of the range limits above.
22. Receiver t
B
is calculated as t
CKR
/10 if no data is being received, or t
CKW
/10 if data is being received. See note.
23. Data includes Q
0−7
, SC/D, and RVS.
24. t
A
, t
ROH
, and t
H
specifications are only valid if all outputs (CKR, RDY, Q
0−7
, SC/D, and RVS) are loaded with similar DC and AC loads.
25. REFCLK has no phase or frequency relationship with CKR and only acts as a centering reference to reduce clock synchronization time. REFCLK must be
within 0.1% of the transmitter CKW frequency, necessitating a ±500-PPM crystal.
26. The PECL switching threshold is the midpoint between the PECL− V
OH
, and V
OL
specification (approximately V
CC
− 1.35V). The TTL switching threshold is 1.5V.
27. Static alignment is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by sliding one bit edge in
3,000 nominal transitions until a byte error occurs.
28. Error Free Window is a measure of the time window between bit centers where a transition may occur without causing a bit sampling error. EFW is measured
over the operating range, input jitter < 50% Dj.
