CY7B92
CY7B93
Document #: 38-02017 Rev. *C Page 7 of 30
logic. Data is transferred to the Framer on each bit, and to the
Decode register once per byte.
Decode Register
The Decode register accepts data from the Shifter once per
byte as determined by the logic in the Clock Synchronization
block. It is presented to the Decoder and held until it is trans-
ferred to the output latch.
Decoder
Parallel data is transformed from ANSI-specified X3.230
8B/10B codes back to “raw data” in the Decoder. This block
uses the standard decoder patterns shown in the Valid Data
Characters and Valid Special Character Codes and
Sequences sections of this datasheet. Data patterns are
signaled by a LOW on the SC/D
output and Special Character
patterns are signaled by a HIGH on the SC/D
output. Unused
patterns or disparity errors are signaled as errors by a HIGH
on the RVS output and by specific Special Character codes.
Output Register
The Output register holds the recovered data (Q
0
-
7
, SC/D, and
RVS) and aligns it with the recovered byte clock (CKR). This
synchronization insures proper timing to match a FIFO interface or
other logic that requires glitch free and specified output behavior.
Outputs change synchronously with the rising edge of CKR.
In BIST mode, this register becomes the signature pattern
generator and checker by logically converting itself into a
Linear Feedback Shift Register (LFSR) pattern generator.
When enabled, this LFSR will generate a 511-byte sequence
that includes all Data and Special Character codes, including
the explicit violation symbols. This pattern provides a
predictable but pseudo-random sequence that can be
matched to an identical LFSR in the Transmitter. When
synchronized, it checks each byte in the Decoder with each
byte generated by the LFSR and shows errors at RVS.
Patterns generated by the LFSR are compared after being
buffered to the output pins and then fed back to the compar-
ators, allowing test of the entire receive function.
In BIST mode, the LFSR is initialized by the first occurrence of
the transmitter BIST loop start code D0.0 (D0.0 is sent only
once per BIST loop). Once the BIST loop has been started,
RVS will be HIGH for pattern mismatches between the
received sequence and the internally generated sequence.
Code rule violations or running disparity errors that occur as
part of the BIST loop will not cause an error indication. RDY
will
pulse HIGH once per BIST loop and can be used to check test
pattern progress. The receiver BIST generator can be reinitialized
by leaving and re-entering BIST mode.
Test Logic
Test logic includes the initialization and control for the Built-In
Self-Test (BIST) generator, the multiplexer for Test mode clock
distribution, and control logic for the decoder. Test logic is
discussed in more detail in the CY7B933 HOTLink Receiver
Operating Mode Description.
HOTLink CY7B923 Transmitter and CY7B933
Receiver Operation
The CY7B923 Transmitter operating with the CY7B933
Receiver form a general purpose data communications
subsystem capable of transporting user data at up to 33
Mbytes per second (40 Mbytes per second for –400 devices)
over several types of serial interface media. Figure 7 illustrates
the flow of data through the HOTLink CY7B923 transmitter pipeline.
Data is latched into the transmitter on the rising edge of CKW
when enabled by ENA
or ENN. RP is asserted LOW with a 60%
LOW/40% HIGH duty cycle when ENA
is LOW. RP may be used as
a read strobe for accessing data stored in a FIFO. The parallel data
flows through the encoder and is then shifted out of the OUTx± PECL
drivers. The bit-rate clock is generated internally from a
multiply-by-ten PLL clock generator. The latency through the
transmitter is approximately 21tB – 10 ns over the operating
range. A more complete description is found in the section
CY7B923 HOTLink Transmitter Operating Mode Description.
Figure 2 illustrates the data flow through the HOTLink
CY7B933 receiver pipeline. Serial data is sampled by the
receiver on the INx± inputs. The receiver PLL locks onto the
serial bit stream and generates an internal bit rate clock. The
bit stream is deserialized, decoded and then presented at the
parallel output pins. A byte rate clock (bit clock ³ 10)
synchronous with the parallel data is presented at the CKR pin.
The RDY
pin will be asserted to LOW to indicate that data or
control characters are present on the outputs. RDY will not be
asserted LOW in a field of K28.5s except for any single K28.5
or the last one in a continuous series of K28.5’s. The latency
through the receiver is approximately 24t
B
+ 10 ns over the
operating range. A more complete description of the receiver
is in the section CY7B933 HOTLink Receiver Operating Mode
Description.
The HOTLink Receiver has a built-in byte framer that synchro-
nizes the Receiver pipeline with incoming SYNC (K28.5)
characters. Figure 3 illustrates the HOTLink CY7B933
Receiver framing operation. The Framer is enabled when the
RF pin is asserted HIGH. RF is latched into the receiver on the
falling edge of CKR. The framer looks for K28.5 characters
embedded in the serial data stream. When a K28.5 is found,
the framer sets the parallel byte boundary for subsequent data
to the K28.5 boundary. While the framer is enabled, the RDY
pin indicates the status of the framing operation.
