OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

CAT9534YI-GT2

P1-P3P4-P6P7-P9P10-P12P13-P14
CAT9534
http://onsemi.com
7
Functional Description
CAT9534’s general purpose input/ output (GPIO)
peripherals provide up to eight I/O ports, controlled through
an I
2
C compatible serial interface.
The CAT9534 supports the I
2
C Bus data transmission
protocol. This I
2
C Bus protocol defines any device that
sends data to the bus to be a transmitter and any device
receiving data to be a receiver. The transfer is controlled by
the Master device which generates the serial clock and all
START and STOP conditions for bus access. The CAT9534
operates as a Slave device. Both the Master device and Slave
device can operate as either transmitter or receiver, but the
Master device controls which mode is activated.
I
2
C Bus Protocol
The features of the I
2
C bus protocol are defined as follows:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition
(Figure 6).
START and STOP Conditions
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT9534 monitors the SDA and
SCL lines and will not respond until this condition is met.
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
Device Addressing
After the bus Master sends a START condition, a slave
address byte is required to enable the CAT9534 for a read or
write operation. The four most significant bits of the slave
address are fixed as binary 0100 and the next three bits are
its individual address bits (Figure 7).
The address bits A2, A1 and A0 are used to select which
device is accessed from maximum eight devices on the same
bus. These bits must compare to their hardwired input pins.
The 8th bit following the 7−bit slave address is the R/W
bit
that specifies whether a read or write operation is to be
performed. When this bit is set to “1”, a read operation is
initiated, and when set to “0”, a write operation is selected.
Following the START condition and the slave address
byte, the CAT9534 monitors the bus and responds with an
acknowledge (on the SDA line) when its address matches
the transmitted slave address. The CAT9534 then performs
a read or a write operation depending on the state of the R/W
bit.
START
CONDITION
STOP
CONDITION
SDA
SCL
Figure 6. START/STOP Condition
0 1 0 0 A2 A1 A0
SLAVE ADDRESS
FIXED PROGRAMMABLE
HARDWARE
SELECTABLE
Figure 7. CAT9534 Slave Address
R/W
CAT9534
http://onsemi.com
8
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data. The SDA line
remains stable LOW during the HIGH period of the
acknowledge related clock pulse (Figure 6).
The CAT9534 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8−bit
byte.
When the CAT9534 begins a READ mode it transmits 8
bits of data, releases the SDA line, and monitors the line for
an acknowledge. Once it receives this acknowledge, the
CAT9534 will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
and waits for a STOP condition. The master must then issue
a STOP condition to return the CAT9534 to the standby
power mode and place the device in a known state.
Registers and Bus Transactions
The CAT9534 consists of an input port register, an output
port register, a polarity inversion register and a
configuration register. Table 7 shows the register address
table. Tables 8 to 11 list Register 0 through Register 3
information.
Table 7. REGISTER COMMAND BYTE
Command
(hex)
Protocol Function
0x00 Read byte Input port register
0x01 Read/write byte Output port register
0x02 Read/write byte Polarity inversion register
0x03 Read/write byte Configuration register
The command byte is the first byte to follow the device
address byte during a write/read bus transaction. The
register command byte acts as a pointer to determine which
register will be written or read.
The input port register is a read only port. It reflects the
incoming logic levels of the I/O pins, regardless of whether
the pin is defined as an input or an output by the
configuration register. Writes to the input port register are
ignored.
Table 8. REGISTER 0 – INPUT PORT REGISTER
bit I
7
I
6
I
5
I
4
I
3
I
2
I
1
I
0
default 1 1 1 1 1 1 1 1
Table 9. REGISTER 1 – OUTPUT PORT REGISTER
bit O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
default 1 1 1 1 1 1 1 1
Table 10. REGISTER 2 –
POLARITY INVERSION REGISTER
bit N
7
N
6
N
5
N
4
N
3
N
2
N
1
N
0
default 0 0 0 0 0 0 0 0
Table 11. REGISTER 3 – CONFIGURATION REGISTER
bit C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
default 1 1 1 1 1 1 1 1
Figure 8. Acknowledge Timing
189
START
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER)
ACK DELAY
ACK SETUP
BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
CAT9534
http://onsemi.com
9
The output port register sets the outgoing logic levels of
the I/O ports, defined as outputs by the configuration
register. Bit values in this register have no effect on I/O pins
defined as inputs. Reads from the output port register reflect
the value that is in the flip−flop controlling the output, not
the actual I/O pin value.
The polarity inversion register allows the user to invert the
polarity of the input port register data. If a bit in this register
is set (“1”) the corresponding input port data is inverted. If
a bit in the polarity inversion register is cleared (“0”), the
original input port polarity is retained.
The configuration register sets the directions of the ports.
Set the bit in the configuration register to enable the
corresponding port pin as an input with a high impedance
output driver. If a bit in this register is cleared, the
corresponding port pin is enabled as an output. At
power−up, the I/Os are configured as inputs with a weak
pull−up resistor to V
CC
.
Data is transmitted to the CAT9534’s registers using the
write mode shown in Figure 9 and Figure 10.
The CAT9534’s registers are read according to the timing
diagrams shown in Figure 11 and Figure 12. Once a
command byte has been sent, the register which was
addressed will continue to be accessed by reads until a new
command byte will be sent.
12345678 9
SCL
SDA
WRITE TO
PORT
DATA OUT FROM PORT
S0100A2 A00
A
A1
00000 001
A
DATA 1 A P
acknowledge from slave
acknowledge from slave
acknowledge
from slave
slave address
command byte data to port
start condition
stop
condition
DATA 1 VALID
Figure 9. Write to Output Port Register
12345678 9
SCL
SDA
WRITE TO
REGISTER
S0100A2 A00
A
A1
00000 011/0
DATA 1
A
A
P
acknowledge from slave
acknowledge from slave
acknowledge
from slave
slave address
command byte data to register
start condition
stop
condition
Figure 10. Write to Configuration or Polarity Inversion Register
R/W
R/W
t
pv
P1-P3P4-P6P7-P9P10-P12P13-P14

CAT9534YI-GT2

Mfr. #:
Buy CAT9534YI-GT2
Manufacturer:
ON Semiconductor
Description:
Interface - I/O Expanders 8B I2C &SMBus I/O PORT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet