© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 0
1 Publication Order Number:
NSTB1002DXV5/D
NSTB1002DXV5T1G,
NSTB1002DXV5T5G
Preferred Devices
Dual Common
Base−Collector Bias
Resistor Transistors
NPN and PNP Silicon Surface Mount
Transistors with Monolithic Bias
Resistor Network
The BRT (Bias Resistor Transistor) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base−emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the NSTB1002DXV5T1G
series, two complementary devices are housed in the SOT−553
package which is ideal for low power surface mount applications
where board space is at a premium.
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• Available in 8 mm, 7 inch Tape and Reel
• These are Pb−Free Devices
MAXIMUM RATINGS (T
A
= 25°C unless otherwise noted, common for Q
1
and Q
2
, − minus sign for Q
1
(PNP) omitted)
Rating Symbo
Value
Unit
Q1 Q2
Collector-Base Voltage V
CBO
−40 50 Vdc
Collector-Emitter Voltage V
CEO
−40 50 Vdc
Collector Current I
C
−200 100 mAdc
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Symbol Max Unit
Total Device Dissipation T
A
= 25°C
Derate above 25°C
P
D
357 (Note 1)
2.9 (Note 1)
mW
mW/°C
Thermal Resistance −
Junction-to-Ambient
R
q
JA
350 (Note 1) °C/W
Characteristic
(Both Junctions Heated)
Symbo
Max Unit
Total Device Dissipation T
A
= 25°C
Derate above 25°C
P
D
500 (Note 1)
4.0 (Note 1)
mW
mW/°C
Thermal Resistance −
Junction-to-Ambient
R
q
JA
250 (Note 1) °C/W
Junction and Storage Temperature T
J
, T
stg
−55 to +150 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. FR−4 @ Minimum Pad
MARKING DIAGRAM
Preferred devices are recommended choices for future use
and best overall value.
45
Q1
Q2
R1
R1
R2
312
http://onsemi.com
SOT−553
CASE 463B
U9 MG
G
1
5
1
5
U9 = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
Device Package Shipping
ORDERING INFORMATION
NSTB1002DXV5T1G SOT−553
(Pb−Free)
4 mm pitch
4000/Tape & Ree
NSTB1002DXV5T5G SOT−553
(Pb−Free)
2 mm pitch
8000/Tape & Ree