PCA9624 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 4.1 — 18 January 2016 10 of 40
NXP Semiconductors
PCA9624
8-bit Fm+ I
2
C-bus 100 mA 40 V LED driver
7.3.1 Mode register 1, MODE1
[1] Bit 4 must be programmed with logic 0 for proper device operation.
[2] It takes 500 s max. for the oscillator to be up and running once SLEEP bit has been set to logic 0. Timings
on LEDn outputs are not guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the
500 s window.
[3] No blinking or dimming is possible when the oscillator is off.
7.3.2 Mode register 2, MODE2
[1] Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9624.
Applicable to registers from 02h (PWM0) to 08h (LEDOUT) only.
[2] Remark: If you change these bits from their default values, the device does not perform as expected.
Table 6. MODE1 - Mode register 1 (address 00h) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 AI2 read only 0 Register Auto-Increment disabled.
1* Register Auto-Increment enabled.
6 AI1 read only 0* Auto-Increment bit 1 = 0.
1 Auto-Increment bit 1 = 1.
5 AI0 read only 0* Auto-Increment bit 0 = 0.
1 Auto-Increment bit 0 = 1.
4 SLEEP
[1]
R/W 0 Normal mode
[2]
.
1* Low-power mode. Oscillator off
[3]
.
3 SUB1 R/W 0* PCA9624 does not respond to I
2
C-bus subaddress 1.
1 PCA9624 responds to I
2
C-bus subaddress 1.
2 SUB2 R/W 0* PCA9624 does not respond to I
2
C-bus subaddress 2.
1 PCA9624 responds to I
2
C-bus subaddress 2.
1 SUB3 R/W 0* PCA9624 does not respond to I
2
C-bus subaddress 3.
1 PCA9624 responds to I
2
C-bus subaddress 3.
0 ALLCALL R/W 0 PCA9624 does not respond to LED All Call I
2
C-bus
address.
1* PCA9624 responds to LED All Call I
2
C-bus address.
Table 7. MODE2 - Mode register 2 (address 01h) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 - read only 0* reserved
6 - read only 0* reserved
5 DMBLNK R/W 0* group control = dimming.
1 group control = blinking.
4 INVRT R/W 0* reserved; write must always be a logic 0
3 OCH R/W 0* outputs change on STOP command
[1]
1 outputs change on ACK
2 - R/W 1* reserved; write must always be a logic 1
[2]
1 - R/W 0* reserved; write must always be a logic 0
[2]
0 - R/W 1* reserved; write must always be a logic 1
[2]
PCA9624 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 4.1 — 18 January 2016 11 of 40
NXP Semiconductors
PCA9624
8-bit Fm+ I
2
C-bus 100 mA 40 V LED driver
7.3.3 PWM0 to PWM7, individual brightness control
A 97 kHz fixed frequency signal is used for each output. Duty cycle is controlled through
256 linear steps from 00h (0 % duty cycle = LED output off) to FFh
(99.6 % duty cycle = LED output at maximum brightness). Applicable to LED outputs
programmed with LDRx = 10 or 11 (LEDOUT0 to LEDOUT3 registers).
(1)
7.3.4 GRPPWM, group duty cycle control
When DMBLNK bit (MODE2 register) is programmed with logic 0, a 190 Hz fixed
frequency signal is superimposed with the 97 kHz individual brightness control signal.
GRPPWM is then used as a global brightness control allowing the LED outputs to be
dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’.
General brightness for the 16 outputs is controlled through 256 linear steps from 00h
(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT3
registers).
When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers
define a global blinking pattern, where GRPFREQ contains the blinking period (from
24 Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
(2)
Table 8. PWM0 to PWM7 - PWM registers 0 to 7 (address 02h to 09h) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
02h PWM0 7:0 IDC0[7:0] R/W 0000 0000* PWM0 Individual Duty Cycle
03h PWM1 7:0 IDC1[7:0] R/W 0000 0000* PWM1 Individual Duty Cycle
04h PWM2 7:0 IDC2[7:0] R/W 0000 0000* PWM2 Individual Duty Cycle
05h PWM3 7:0 IDC3[7:0] R/W 0000 0000* PWM3 Individual Duty Cycle
06h PWM4 7:0 IDC4[7:0] R/W 0000 0000* PWM4 Individual Duty Cycle
07h PWM5 7:0 IDC5[7:0] R/W 0000 0000* PWM5 Individual Duty Cycle
08h PWM6 7:0 IDC6[7:0] R/W 0000 0000* PWM6 Individual Duty Cycle
09h PWM7 7:0 IDC7[7:0] R/W 0000 0000* PWM7 Individual Duty Cycle
duty cycle
IDCx 7:0
256
---------------------------
=
Table 9. GRPPWM - Group brightness control register (address 0Ah) bit description
Legend: * default value
Address Register Bit Symbol Access Value Description
0Ah GRPPWM 7:0 GDC[7:0] R/W 1111 1111 GRPPWM register
duty cycle
GDC 7:0
256
--------------------------
=
PCA9624 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 4.1 — 18 January 2016 12 of 40
NXP Semiconductors
PCA9624
8-bit Fm+ I
2
C-bus 100 mA 40 V LED driver
7.3.5 GRPFREQ, group frequency
GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2
register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT3
registers).
Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz)
to FFh (10.73 s).
(3)
7.3.6 LEDOUT0 and LEDOUT1, LED driver output state
LDRx = 00 — LED driver x is off (default power-up state).
LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking
not controlled).
LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx
register.
LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be
controlled through its PWMx register and the GRPPWM registers.
Table 10. GRPFREQ - Group Frequency register (address 0Bh) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
0Bh GRPFREQ 7:0 GFRQ[7:0] R/W 0000 0000* GRPFREQ register
global blinking period
GFRQ 7:01+
24
----------------------------------------
s=
Table 11. LEDOUT0 to LEDOUT1 - LED driver output state register (address 0Ch to 0Dh)
bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
0Ch LEDOUT0 7:6 LDR3 R/W 00* LED3 output state control
5:4 LDR2 R/W 00* LED2 output state control
3:2 LDR1 R/W 00* LED1 output state control
1:0 LDR0 R/W 00* LED0 output state control
0Dh LEDOUT1 7:6 LDR7 R/W 00* LED7 output state control
5:4 LDR6 R/W 00* LED6 output state control
3:2 LDR5 R/W 00* LED5 output state control
1:0 LDR4 R/W 00* LED4 output state control

PCA9624BS,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
LED Lighting Drivers 8-BIT FM+ I2C-BUS 100 MA 40V LED DRVR
Lifecycle:
New from this manufacturer.
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