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IDT72V36103L10PF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
7
COMMERCIAL TEMPERATURE RANGE
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFO
TM
WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3683/72V3693/72V36103 with CLKA
and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected
to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of IDT72V3683/72V3693/72V36103
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x ICC(f) + Σ(CL x VCC
2
x fo)
N
where:
N = number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus size)
CL = output capacitance load
fo = switching frequency of an output
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
010203040506070
0
10
20
30
40
50
60
fS
⎯
Clock Frequency
⎯
MHz
ICC(f) Supply Current mA
fdata = 1/2 fS
TA = 25°C
C
L = 0 pF
4678 drw 03
70
90
80
100
80
90
100
VCC = 3.3V
V
CC = 3.6V
V
CC = 3.0V
8
COMMERCIAL TEMPERATURE RANGE
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFO
TM
WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
IDT72V3683L10 IDT72V3683L15
IDT72V3693L10 IDT72V3693L15
IDT72V36103L10 IDT72V36103L15
Symbol Parameter Min. Max. Min. Max. Unit
fS Clock Frequency, CLKA or CLKB — 100 — 66.7 MHz
tCLK Clock Cycle Time, CLKA or CLKB 10 — 15 — ns
tCLKH Pulse Duration, CLKA or CLKB HIGH 4.5 — 6 — ns
tCLKL Pulse Duration, CLKA and CLKB LOW 4.5 — 6 — ns
tDS Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑ 3— 4—ns
tENS1 Setup Time, CSA and W/RA before CLKA↑; CSB and W/RB before CLKB↑ 4 — 4.5 — ns
tENS2 Setup Time, ENA, and MBA before CLKA↑; ENB and MBB before CLKB↑ 3 — 4.5 — ns
tRSTS Setup Time, RS1 or PRS LOW before CLKA↑ or CLKB↑
(1)
5— 5—ns
tFSS Setup Time, FS0, FS1 and FS2 before RS1 HIGH 7.5 — 7.5 — ns
tBES Setup Time, BE/FWFT before RS1 HIGH 7.5 — 7.5 — ns
tSDS Setup Time, FS0/SD before CLKA↑ 3— 4—ns
tSENS Setup Time, FS1/SEN before CLKA↑ 3— 4—ns
tFWS Setup Time, FWFT before CLKA↑ 0— 0—ns
tDH Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑ 0.5 — 1 — ns
tRTMS Setup Time, RTM before RT1; RTM before RT2 5— 5—ns
tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, and MBB 0.5 — 1 — ns
after CLKB↑
tRSTH Hold Time, RS1 or PRS LOW after CLKA↑ or CLKB↑
(1)
4— 4—ns
tFSH Hold Time, FS0, FS1 and FS2 after RS1 HIGH 2 — 2 — ns
tBEH Hold Time, BE/FWFT after RS1 HIGH 2 — 2 — ns
tSDH Hold Time, FS0/SD after CLKA↑ 0.5 — 1 — ns
tSENH Hold Time, FS1/SEN HIGH after CLKA↑ 0.5 — 1 — ns
tSPH Hold Time, FS1/SEN HIGH after RS1 HIGH 2 — 2 — ns
tRTMH Hold Time, RTM after RT1; RTM after RT2 5— 5—ns
tSKEW1
(2)
Skew Time between CLKA↑ and CLKB↑ for EF/OR and FF/IR 5 — 7.5 — ns
tSKEW2
(2,3)
Skew Time between CLKA↑ and CLKB↑ for AE and AF 12 — 12 — ns
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
3. Design simulated, not tested.
(Vcc = 3.3V ± 0.15V; TA = 0
ο
C to +70
ο
C; JEDEC JESD8-A compliant)
9
COMMERCIAL TEMPERATURE RANGE
IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFO
TM
WITH
BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36
IDT72V3683L10 IDT72V3683L15
IDT72V3693L10 IDT72V3693L15
IDT72V36103L10 IDT72V36103L15
Symbol Parameter Min. Max. Min. Max. Unit
tA Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35 2 6.5 2 10 ns
tWFF Propagation Delay Time, CLKA↑ to FF/IR 2 6.5 2 8 ns
tREF Propagation Delay Time, CLKB↑ to EF/OR 1 6.5 1 8 ns
tPAE Propagation Delay Time, CLKB↑ to AE 1 6.5 1 8 ns
tPAF Propagation Delay Time, CLKA↑ to AF 1 6.5 1 8 ns
tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 and CLKB↑ to MBF2 0 6.5 0 8 ns
LOW or MBF1 HIGH
tPMR Propagation Delay Time, CLKA↑ to B0-B35
(1)
and CLKB↑ to A0-A35
(2)
28 210ns
tMDV Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 Valid 2 6.5 2 10 ns
t
RSF Propagation Delay Time, RS1 or PRS LOW to AE LOW, AF HIGH, MBF1 HIGH 1 10 1 15 ns
and MBF2 HIGH
tEN Enable Time, CSA and W/RA LOW to A0-A35 Active and CSB LOW and W/RB HIGH 2 6 2 10 ns
to B0-B35 Active
tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and CSB HIGH 1 6 1 8 ns
or W/RB LOW to B0-B35 at high-impedance
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C
L = 30 pF
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
(Vcc = 3.3V ± 0.15V; TA = 0
ο
C to +70
ο
C; JEDEC JESD8-A compliant)
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IDT72V36103L10PF

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IC FIFO 131X18 10NS 128QFP
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