REVISION B 7/10/15
8536I-33 DATA SHEET
7 LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-
3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER
TABLE 6C. LVCMOS AC CHARACTERISTICS, V
CC
= V
CCO_LVCMOS
= 3.3V±5%, TA = -40°C TO 85°C
TABLE 6D. LVCMOS AC CHARACTERISTICS, V
CC
= V
CCO_LVCMOS
= 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 266 MHz
t
PD
Propagation Delay; NOTE 1 2.4 3.5 ns
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
155.52MHz,
(Integration Range:
12kHz - 20MHz)
0.35 ps
tsk(b) Bank Skew; NOTE 2, 5 65 ps
tsk(o) Output Skew; NOTE 3, 5 80 ps
tsk(pp) Part-to-Part Skew; NOTE 4, 5 0.730 800 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 0.3 1.15 ns
odc Output Duty Cycle 46 54 %
All parameters measured at ƒ ≤ 266MHz unless noted otherwise.
NOTE 1: Measured from the V
CC
/2 of the input to V
CCO_LVCMOS
/2 of the output.
NOTE 2: Defi ned as skew within a bank of outputs at the same voltage and with equal load conditions.
NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
CCO_LVCMOS
/2.
NOTE 4: Defi ned as skew between outputs on different devices operating at the same supply voltage and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at V
CCO_LVCMOS
/2.
NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 266 MHz
t
PD
Propagation Delay; NOTE 1 2.5 3.75 ns
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
155.52MHz,
(Integration Range:
12kHz - 20MHz)
0.32 ps
tsk(b) Bank Skew; NOTE 2, 5 75 ps
tsk(o) Output Skew; NOTE 3, 5 80 ps
tsk(pp) Part-to-Part Skew; NOTE 4, 5 800 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 0.425 1.85 ns
odc Output Duty Cycle 46 54 %
All parameters measured at ƒ ≤ 266MHz unless noted otherwise.
NOTE 1: Measured from the V
CC
/2 of the input to V
CCO_LVCMOS
/2 of the output.
NOTE 2: Defi ned as skew within a bank of outputs at the same voltage and with equal load conditions.
NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
CCO_LVCMOS
/2.
NOTE 4: Defi ned as skew between outputs on different devices operating at the same supply voltage and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at V
CCO_LVCMOS
/2.
NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65.
