AD9575
Rev. A | Page 12 of 16
THEORY OF OPERATION
XTAL
OSC
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
1/n 1/k
SEL
LVCMOS
CMOS OUT/SEL1
DDX GNDX
DD
GNDA
DD_CMOS GND_CMOS
SEL0
1/m
V
LDO
2.488GHz TO
2.55GHz VCO
LVDS
100MHz
AD9575
08462-015
LDO
LVDS/LVPECL OUT
LVDS/LVPECL OUT
Figure 17. Detailed Block Diagram
Figure 17 shows a block diagram of the AD9575. The chip features
a PLL core, which is configured to generate the specific clock
frequencies via pin programming. By appropriate connection of
the select pins, SEL0 and SEL1, the divide ratios of the feedback
divider (n), LVDS output divider (m), and LVCMOS output
divider (k) can be programmed (see Table 1 2). In Mode 1 and
Mode 4, Pin 10 is configured as an LVCMOS output by forcing
Pin 16 to GND (33.33 MHz output) or by leaving Pin 16 uncon-
nected (62.5 MHz output). In conjunction with a band-select
VCO that operates over the range of 2.488 GHz to 2.55 GHz,
a wide range of popular network reference frequencies can
be generated. This PLL is based on proven Analog Devices
synthesizer technology, noted for its exceptional phase noise
performance. The AD9575 is highly integrated and includes
the loop filter, a regulator for supply noise immunity, all the
necessary dividers, output buffers, and a crystal oscillator. A
user need only supply an external crystal to implement a
clocking solution that requires no processor intervention.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the reference clock and feedback
divider to produce an output proportional to the phase and
frequency difference between them. Figure 18 shows a
simplified schematic.
08462-016
D1 Q1
CLR1
REFCLK
HIGH
UP
D2 Q2
CLR2
HIGH
DOWN
CP
CHARGE
PUMP
P
GND
FEEDBACK
DIVIDER
Figure 18. PFD Simplified Schematic
POWER SUPPLY
The AD9575 requires a 3.3 V ± 10% power supply for V
S
. The
Specifications section gives the performance expected from the
AD9575 with the power supply voltage within this range. The
absolute maximum range of −0.3 V to +3.6 V, with respect to
GND, must never be exceeded on the VDD, VDDA, VDDX,
and VDD_CMOS pins.
Good engineering practice should be followed in the layout
of power supply traces and the ground plane of the PCB. The
power supply should be bypassed on the PCB with adequate
capacitance (>10 μF). The AD9575 should be bypassed with
adequate capacitors (0.1 μF) at all power pins as close as possible
to the part. The layout of the AD9575 evaluation board is a
good example.
LVPECL CLOCK DISTRIBUTION
Because they are open emitter, the LVPECL outputs require
a dc termination to bias the output transistors. The simplified
equivalent circuit in Figure 19 shows the LVPECL output stage.
08462-026
LVPECL
TERM
LVPECL
50Ω 50Ω
50Ω
50Ω
0.1µF
0.1µF
200Ω 200Ω
Figure 19. LVPECL AC-Coupled Termination
In most applications, a standard LVPECL far-end termination is
recommended, as shown in Figure 20. The resistor network is
designed to match the transmission line impedance (50 Ω) and
the desired switching threshold (1.3 V).
