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AD9575ARUZPEC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
AD9575
Rev. A | Page 3 of 16
SPECIFICATIONS
Typical (typ) values are given for V
S
= 3.3 V ± 10%, T
A
= 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are
given over the full V
S
and T
A
(−40°C to +85°C) variation.
PLL CHARACTERISTICS
Table 1.
LVDS LVCMOS LVPECL
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
PHASE NOISE CHARACTERISTICS
PLL Noise (100 MHz Output)
At 1 kHz −123 −122 dBc/Hz
At 10 kHz −128 −129 dBc/Hz
At 100 kHz −131 −131 dBc/Hz
At 1 MHz −150 −151 dBc/Hz
At 10 MHz −156 −158 dBc/Hz
At 30 MHz −156 −158 dBc/Hz
PLL Noise (106.25 MHz Output)
At 1 kHz −121 −121 dBc/Hz
At 10 kHz −127 −128 dBc/Hz
At 100 kHz −130 −130 dBc/Hz
At 1 MHz −149 −150 dBc/Hz
At 10 MHz −156 −158 dBc/Hz
At 30 MHz −156 −159 dBc/Hz
PLL Noise (125 MHz Output)
At 1 kHz −120 −120 dBc/Hz
At 10 kHz −126 −127 dBc/Hz
At 100 kHz −128 −129 dBc/Hz
At 1 MHz −148 −150 dBc/Hz
At 10 MHz −155 −157 dBc/Hz
At 30 MHz −156 −158 dBc/Hz
PLL Noise (155.52 MHz Output)
At 1 kHz −118 −118 dBc/Hz
At 10 kHz −123 −123 dBc/Hz
At 100 kHz −125 −125 dBc/Hz
At 1 MHz −147 −149 dBc/Hz
At 10 MHz −155 −157 dBc/Hz
At 30 MHz −156 −157 dBc/Hz
PLL Noise (156.25 MHz Output)
At 1 kHz −118 −118 dBc/Hz
At 10 kHz −124 −125 dBc/Hz
At 100 kHz −126 −127 dBc/Hz
At 1 MHz −146 −148 dBc/Hz
At 10 MHz −155 −157 dBc/Hz
At 30 MHz −155 −157 dBc/Hz
PLL Noise (159.375 MHz Output)
At 1 kHz −118 −118 dBc/Hz
At 10 kHz −124 −125 dBc/Hz
At 100 kHz −126 −126 dBc/Hz
At 1 MHz −146 −147 dBc/Hz
At 10 MHz −155 −156 dBc/Hz
At 30 MHz −155 −157 dBc/Hz
AD9575
Rev. A | Page 4 of 16
LVDS LVCMOS LVPECL
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
PLL Noise (161.132812 MHz Output)
At 1 kHz −118 −119 dBc/Hz
At 10 kHz −122 −123 dBc/Hz
At 100 kHz −126 −126 dBc/Hz
At 1 MHz −144 −146 dBc/Hz
At 10 MHz −154 −156 dBc/Hz
At 30 MHz −155 −156 dBc/Hz
PLL Noise (312.5 MHz Output)
At 1 kHz −112 −112 dBc/Hz
At 10 kHz −119 −119 dBc/Hz
At 100 kHz −120 −120 dBc/Hz
At 1 MHz −140 −142 dBc/Hz
At 10 MHz −152 −154 dBc/Hz
At 30 MHz −153 −155 dBc/Hz
PLL Noise (33.33 MHz Output)
At 1 kHz −131 dBc/Hz
At 10 kHz −138 dBc/Hz
At 100 kHz −140 dBc/Hz
At 1 MHz −155 dBc/Hz
At 5 MHz −155 dBc/Hz
PLL Noise (62.5 MHz Output)
At 1 kHz −126 dBc/Hz
At 10 kHz −133 dBc/Hz
At 100 kHz −134 dBc/Hz
At 1 MHz −150 dBc/Hz
At 5 MHz −152 dBc/Hz
Spurious Content −70 −70 dBc
PLL Figure of Merit −217 −217 dBc/Hz
LVDS CLOCK OUTPUT JITTER (TYP/MAX)
Typical (typ) values are given for V
S
= 3.3 V ± 10%, T
A
= 25°C, unless otherwise noted. Maximum (max) values are given over the full V
S
and T
A
(−40°C to +85°C) variation.
Table 2.
Jitter Integration
Bandwidth
100
MHz
106.25
MHz
125
MHz
155.52
MHz
156.25
MHz
159.375
MHz
161.13
MHz
312.5
MHz Unit
12 kHz to 20 MHz 0.38/0.50 0.40/0.54 0.37/0.47 0.41/0.54 0.39/0.51 0.38/0.51 0.44/0.61 0.36/0.48 ps rms
1.875 MHz to 20 MHz 0.15/0.27 ps rms
637 kHz to 10 MHz 0.15/0.21 ps rms
LVPECL CLOCK OUTPUT JITTER (TYP/MAX)
Typical (typ) values are given for V
S
= 3.3 V ± 10%, T
A
= 25°C, unless otherwise noted. Maximum (max) values are given over the full V
S
and T
A
(−40°C to +85°C) variation.
Table 3.
Jitter Integration
Bandwidth
100
MHz
106.25
MHz
125
MHz
155.52
MHz
156.25
MHz
159.375
MHz
161.13
MHz
312.5
MHz
Unit
12 kHz to 20 MHz 0.36/0.46 0.44/0.68 0.36/0.45 0.40/0.52 0.39/0.64 0.41/0.62 0.43/0.69 0.38/0.49 ps rms
1.875 MHz to 20 MHz 0.19/0.54 ps rms
637 kHz to 10 MHz 0.22/0.35 ps rms
AD9575
Rev. A | Page 5 of 16
OUTPUT FREQUENCY SELECT
Minimum (min) and maximum (max) values are given over the full V
S
and T
A
(−40°C to +85°C) variation.
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
Select Pins (SEL0/SEL1)
Logic 1 Voltage 0.83 × V
S
+ 0.2 V
Logic 0 Voltage 0.33 × V
S
− 0.2 V
Logic 1 Current 190 μA Pull-up to V
S
Logic 0 Current 150 μA Pull-down to GND
CLOCK OUTPUTS
Typical (typ) values are given for V
S
= 3.3 V ± 10%, T
A
= 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are
given over the full V
S
and T
A
(−40°C to +85°C) variation.
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
LVDS CLOCK OUTPUT Termination = 100 Ω differential; default
Output Frequency 312.5 MHz
Differential Output Voltage (V
OD
) 250 340 450 mV See Figure 2 for definition
Delta V
OD
25 mV
Output Offset Voltage (V
OS
) 1.125 1.25 1.375 V
Delta V
OS
25 mV
Short-Circuit Current (I
SA
, I
SB
) 14 24 mA Output shorted to GND
Duty Cycle 45 50 55 %
LVPECL CLOCK OUTPUT
Output Frequency 312.5 MHz
Output High Voltage (V
OH
) V
S
− 1.5 V
S
− 1.05 V
S
− 0.8 V
Output Low Voltage (V
OL
) V
S
− 2.5 V
S
− 1.75 V
S
− 1.7 V
Differential Output Voltage (V
OD
) 430 640 800 mV See Figure 2 for definition
Duty Cycle 45 50 55 %
LVCMOS CLOCK OUTPUT
Output Frequency 62.5 MHz
Output High Voltage (V
OH
) V
S
− 0.1 V
Output Low Voltage (V
OL
) 0.1 V
Duty Cycle 45 50 55 %
TIMING CHARACTERISTICS
Table 6.
Parameter Min Typ Max Unit Test Conditions/Comments
LVDS
Termination = 100 Ω differential; C
LOAD
= 0 pF;
C
AC
= 0.1 μF
Output Rise Time, t
RL
150 200 300 ps 20% to 80%, measured differentially
Output Fall Time, t
FL
150 200 300 ps 80% to 20%, measured differentially
LVPECL
Termination = 200 Ω to GND; C
LOAD
= 0 pF;
C
AC
= 0.1 μF
Output Rise Time, t
RL
180 250 300 ps 20% to 80%, measured differentially
Output Fall Time, t
FL
180 250 300 ps 80% to 20%, measured differentially
LVCMOS
Termination = 50 Ω to 0 V; C
LOAD
= 5 pF;
C
AC
= 0.1 μF
Output Rise Time, t
RC
0.50 0.70 1.10 ns 20% to 80%
Output Fall Time, t
FC
0.50 0.70 1.10 ns 80% to 20%
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD9575ARUZPEC

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Buy AD9575ARUZPEC
Manufacturer:
Analog Devices Inc.
Description:
Clock Generators & Support Products PCI-Express PLL Core 2 Outputs
Lifecycle:
New from this manufacturer.
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