74ABT652CMSAX

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74ABT652
Skew
(SOIC Package)
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH to LOW (t
OSHL
), LOW-to-HIGH (t
OSLH
), or any combination switching LOW-to-HIGH and/or HIGH-to-
LOW (t
OST
). This specification is guaranteed but not tested.
Note 15: Propagation delay variation for a given set of conditions (i.e., temperature and V
CC
) from device to device. This specification is guaranteed but not
tested
Note 16: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.).
Note 17: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 18: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Capacitance
Note 19: C
I/O
is measured at frequency, f = 1 MHz, per MIL-STD-883D, Method 3012.
Symbol Parameter
T
A
= 40°C to +85°CT
A
= 40°C to +85°C
Units
V
CC
= 4.5V–5.5V V
CC
= 4.5V–5.5V
C
L
= 50 pF C
L
= 250 pF
8 Outputs Switching 8 Outputs Switching
(Note 16) (Note 17)
Max Max
t
OSHL
Pin to Pin Skew 1.3 2.5 ns
(Note 14) HL Transitions
t
OSLH
Pin to Pin Skew 1.0 2.0 ns
(Note 14) LH Transitions
t
PS
Duty Cycle 2.0 4.0 ns
(Note 18) LH–HL Skew
t
OST
Pin to Pin Skew 2.0 4.0 ns
(Note 14) LH/HL Transitions
t
PV
Device to Device Skew 2.5 4.5 ns
(Note 15) LH/HL Transitions
Symbol Parameter Typ Units
Conditions
(T
A
= 25°C)
C
IN
Input Capacitance 5.0 pF V
CC
= 0V (non I/O pins)
C
I/O
(Note 19) I/O Capacitance 11.0 pF V
CC
= 5.0V (A
n
, B
n
)
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74ABT652
AC Loading
*Includes jig and probe capacitance
FIGURE 2. Standard AC Test Load
FIGURE 3. Test Input Signal Levels
Input Pulse Requirements
FIGURE 4. Test Input Signal Requirements
AC Waveforms
FIGURE 5. Propagation Delay Waveforms
for Inverting and Non-Inverting Functions
FIGURE 6. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 8. Setup Time, Hold Time
and Recovery Time Waveforms
Amplitude Rep. Rate t
W
t
r
t
f
3.0V 1 MHz 500 ns 2.5 ns 2.5 ns
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74ABT652
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M24B
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA24

74ABT652CMSAX

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Bus Transceivers Octal Trans and Reg
Lifecycle:
New from this manufacturer.
Delivery:
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