Continuous Rate 10 Mb/s to 675 Mb/s Clock and
Data Recovery IC with Integrated Limiting Amp
Data Sheet
ADN2814
Rev. C
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FEATURES
Serial data input: 10 Mb/s to 675 Mb/s
Exceeds SONET requirements for jitter transfer/
generation/tolerance
Quantizer sensitivity: 3.3 mV typical
Adjustable slice level: ±95 mV
Patented clock recovery architecture
Loss-of-signal (LOS) detect range: 2.3 mV to 19 mV
Independent slice level adjust and LOS detector
No reference clock required
Loss-of-lock indicator
I
2
C® interface to access optional features
Single-supply operation: 3.3 V
Low power: 435 mW typical
5 mm × 5 mm, 32-lead LFCSP, Pb free
APPLICATIONS
SONET OC-1/-3/-12 and all associated FEC rates
ESCON, Fast Ethernet, serial digital interfaces (DTV)
WDM transponders
Regenerators/repeaters
Test equipment
Broadband cross-connects and routers
GENERAL DESCRIPTION
The ADN2814 provides the receiver functions of quantization,
signal level detect, and clock and data recovery for continuous
data rates from 10 Mb/s to 675 Mb/s. The ADN2814 automati-
cally locks to all data rates without the need for an external
reference clock or programming. All SONET jitter requirements
are met, including jitter transfer, jitter generation, and jitter
tolerance. All specifications are quoted for −40°C to +85°C
ambient temperature, unless otherwise noted.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power fiber
optic receiver.
The receiver front-end, loss-of-signal (LOS) detector circuit
indicates when the input signal level has fallen below a user-
adjustable threshold. The LOS detect circuit has hysteresis to
prevent chatter at the output.
The ADN2814 is available in a compact 5 mm × 5 mm,
32-lead LFCSP.
FUNCTIONAL BLOCK DIAGRAM
2
SLICEP/SLICEN
LOL
DATAOUTP/
DATAOUTN
LOSTHRADJ CLKOUTP/
CLKOUTN
ADN2814
2
VCC VEECF1 CF2
PIN
NIN
VREF
QUANTIZER
VCO
PHASE
SHIFTER
PHASE
DETECT
FREQUENCY
DETECT
LOS
DETECT
DATA
RE-TIMING
LOOP
FILTER
LOOP
FILTER
REFCLKP/REFCLKN
(OPTIONAL)
2
04949-001
Figure 1.
ADN2814* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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EVALUATION KITS
ADN2814 Evaluation Board
DOCUMENTATION
Application Notes
AN-657: ADN2812 Evaluation Board
Data Sheet
ADN2814: Continuous Rate 10 Mb/s to 675 Mb/s Clock
and Data Recovery IC with Integrated Limiting Amp Data
Sheet
REFERENCE MATERIALS
Informational
Optical and High Speed Networking ICs
DESIGN RESOURCES
ADN2814 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
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SAMPLE AND BUY
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ADN2814 Data Sheet
Rev. C | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Jitter Specifications....................................................................... 4
Output and Timing Specifications............................................. 5
Absolute Maximum Ratings............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution.................................................................................. 6
Timing Characteristics..................................................................... 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
I
2
C Interface Timing and Internal Register Description........... 10
Terminology .................................................................................... 12
Jitter Specifications......................................................................... 13
Theory of Operation ...................................................................... 14
Functional Description.................................................................. 16
Frequency Acquisition............................................................... 16
Limiting Amplifier ..................................................................... 16
Slice Adjust.................................................................................. 16
Loss-of-Signal (LOS) Detector ................................................. 16
Lock Detector Operation .......................................................... 17
Harmonic Detector .................................................................... 17
SQUELCH Mode........................................................................ 18
I
2
C Interface ................................................................................ 18
Reference Clock (Optional) ...................................................... 18
Applications Information.............................................................. 21
PCB Design Guidelines ............................................................. 21
DC-Coupled Application .......................................................... 23
Coarse Data Rate Readback Look-Up Table............................... 24
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
REVISION HISTORY
3/12—Rev. B to Rev. C
Updated Outline Dimensions....................................................... 26
Changes to Ordering Guide .......................................................... 26
5/10—Rev. A to Rev. B
Changes to Figure 5 and Table 5..................................................... 8
Changes to Figure 24...................................................................... 21
Added Exposed Pad Notation to Outline Dimensions ............. 26
3/09—Rev. 0 to Rev. A
Updated Outline Dimensions....................................................... 26
Changes to Ordering Guide .......................................................... 26
9/05—Revision 0: Initial Version

ADN2814ACPZ-500RL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Timers & Support Products 12 Mbps - 1.3G ADN2812 Derivative IC.
Lifecycle:
New from this manufacturer.
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